Micron Technology Inc v. Yangtze Memory Technologies Co Ltd

1. Case Identification

• Case #: IPR2024-00795
• Patent #: 11,501,822
• Filed: April 11, 2024
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Yangtze Memory Technologies Company, Ltd.
• Challenged Claims: 1-9 and 11-19

2. Patent Overview

• Title: Non-Volatile Memory Device and Control Method
• Brief Description: The ’822 patent relates to 3D NAND flash memory devices and methods for controlling them. The invention aims to reduce "program disturb"—the inadvertent programming of unselected memory cells—by applying different pre-pulse voltage signals to different groups of unselected word lines during a pre-charge period.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 6, and 11-13 are obvious over Lee

• Prior Art Relied Upon: Lee (Patent 10,121,529).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Lee teaches a 3D NAND memory device that addresses program disturb by grouping word lines and applying different pre-bias voltages during a pre-charge step. Specifically, Lee discloses arranging word lines into multiple groups (e.g., four groups) and applying increasingly higher pre-bias voltages to groups that are closer to the drain select transistor. Petitioner contended this directly maps to the limitations of independent claims 1 and 11, which require applying first, second, and third pre-pulse signals to corresponding groups of word lines. Lee's teaching that the voltage increases with proximity to the drain select transistor was argued to render the ordering and increasing voltage limitations of dependent claims 2-3 and 12-13 obvious.
  • Motivation to Combine (for §103 grounds): Not applicable (single reference ground). The motivation is inherent in Lee's own teachings.
  • Expectation of Success (for §103 grounds): Petitioner asserted that a Person of Ordinary Skill in the Art (POSITA) would have had an expectation of success because Lee explicitly teaches this method to mitigate the known problem of program disturb by accounting for the resistance component along a memory string's channel.

Ground 2: Claims 1, 4-7, 9, 11, 14-16, and 18-19 are obvious over Zhao

• Prior Art Relied Upon: Zhao (Patent 10,643,718).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Zhao discloses a 3D NAND memory system that applies different pre-charge voltages to different groups of word lines to avoid program disturb. Zhao teaches grouping unprogrammed word lines on the "drain side" of a selected word line to receive one pre-charge voltage (Vprecharge), multiple "already programmed" word lines on the "source side" adjacent to the selected word line to receive a higher "bypass voltage" (Vbypass), and the remaining source-side word lines to receive a "low" pre-charge voltage (Vss). Petitioner argued this constitutes the claimed "first," "second," and "third" groups receiving different pre-pulse signals, as required by independent claims 1 and 11. Zhao also discloses applying signals to dummy word lines, mapping to dependent claims 7 and 16.
  • Motivation to Combine (for §103 grounds): Not applicable (single reference ground). The motivation is inherent in Zhao's own teachings.
  • Expectation of Success (for §103 grounds): A POSITA would have expected success as Zhao's stated purpose for using these different voltages is to equalize charge across the channel and assist in avoiding program disturb.

Ground 3: Claims 1-9 and 11-19 are obvious over Zhao in view of Lee

• Prior Art Relied Upon: Zhao (Patent 10,643,718) and Lee (Patent 10,121,529).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Zhao teaches applying a single pre-charge voltage (Vprecharge) to all unselected word lines on the drain-side of the selected word line. Lee was argued to improve upon this approach by teaching that program disturb can be more effectively mitigated by accounting for channel resistance. Lee's solution is to subdivide the drain-side word lines into multiple groups and apply increasingly higher pre-bias voltages to groups located further from the selected word line (i.e., closer to the drain select transistor).
  • Motivation to Combine (for §103 grounds): A POSITA would combine Lee's teachings with Zhao's system to improve its performance. Petitioner argued that while Zhao addresses some sources of program disturb, it fails to account for channel resistance, which Lee explicitly addresses. A POSITA would recognize that applying Lee’s graduated voltage scheme to the drain-side word lines in Zhao’s memory would result in more uniform pre-charging, better boosting, and reduced program disturb, which is a shared goal of both references.
  • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because the combination amounts to a straightforward application of Lee's known technique for improving program disturb mitigation to Zhao's compatible 3D NAND architecture.

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) based on Yang (Patent 10,726,920), which was presented as another example of a prior art reference that applies different pre-charge voltages to different groups of word lines based on their position and programming status to reduce program disturb.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) based on Fintiv factors. It was asserted that the parallel district court trial date (December 1, 2025) is well after the statutory deadline for a Final Written Decision (FWD), minimal investment has occurred in the parallel proceeding, and Petitioner stipulated it would not advance the same invalidity grounds in district court, eliminating issue overlap.
• Petitioner also argued against denial under §325(d), contending that the primary references (Lee, Zhao, and Yang) were not considered by the Examiner during prosecution of the ’822 patent. It was argued these references are meaningfully different from the art of record because they teach applying at least three different pre-charge voltages, whereas the Examiner previously considered art teaching only two.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-9 and 11-19 of the ’822 patent as unpatentable.