PTAB

IPR2024-00803

Aptiv Services US LLC v. Microchip Technology Inc

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1. Case Identification

2. Patent Overview

  • Title: Circuit for Protection Against Electrostatic Discharge
  • Brief Description: The ’665 patent discloses a circuit for protecting integrated circuits from electrostatic discharge (ESD). The invention connects an input/output (I/O) pad to a voltage rail during an ESD event, allowing the inherent capacitance of other pads in the system to charge and absorb ESD energy, thereby reducing the peak voltage experienced by the circuit.

3. Grounds for Unpatentability

Ground 1: Claims 1-18 are obvious over Verhaege

  • Prior Art Relied Upon: Verhaege (Patent 6,529,359).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Verhaege discloses a complete ESD protection circuit meeting the limitations of the independent claims. Specifically, Verhaege’s gate clamp 44 was identified as the claimed "control block," and its dynamic trigger device 42 as the "enable circuitry." During an ESD event, this enable circuitry instructs the control block to turn on PMOS output transistor 14, connecting the I/O pad to the Vdd rail. Petitioner asserted that although Verhaege illustrates a single pad circuit, a POSITA would have found it obvious to replicate this circuit at every I/O pad on an integrated circuit, as was standard practice. In such a multi-pad system, activating one PMOS transistor connects its pad to the Vdd rail, allowing ESD energy to flow to and charge the inherent capacitance of all other pads also connected to that rail, thereby reducing the maximum system voltage. Verhaege’s ESD clamp 40 was mapped to the "clamp device" limitation.
    • Motivation to Combine: Not applicable for this single-reference ground. The argument relied on the motivation to apply a known protection scheme to all vulnerable points (I/O pads) in a system, which was a predictable and common design choice.
    • Expectation of Success: A POSITA would have had a high expectation of success because all circuit components were conventional, and applying protection comprehensively was a well-established method for improving ESD robustness.

Ground 2: Claims 1-18 are obvious over Verhaege in view of Miller

  • Prior Art Relied Upon: Verhaege (Patent 6,529,359), Miller (Patent 7,589,945).
  • Core Argument for this Ground:
    • Prior Art Mapping: Verhaege was asserted to provide the fundamental pad-level ESD circuit, as detailed in Ground 1. Miller was cited for its teaching of a distributed, system-level ESD protection strategy where multiple pad circuits are connected in parallel and activated simultaneously via a common trigger rail 350. Miller’s system explicitly coordinates multiple clamp transistors to "work together to dissipate the ESD currents." The proposed combination applies Verhaege's circuit at each I/O pad within Miller's multi-pad, parallel architecture.
    • Motivation to Combine: Petitioner contended that a POSITA addressing the well-known problem of ESD would combine these references to gain the benefits of both: Verhaege's specific transistor control logic and Miller's superior system-wide energy distribution. Implementing Miller’s strategy would require only a simple modification to Verhaege—connecting the trigger devices to a common line as taught by Miller—to activate multiple pad circuits during an ESD event. Petitioner also noted that Miller’s optional "ESD boost" rail teaches the use of a separate voltage rail, rendering claims requiring separate rails obvious.
    • Expectation of Success: The combination was argued to be predictable, as the circuit elements in both references were standard and their interaction well-understood. The modification to Verhaege's circuit was presented as minor and would foreseeably yield the desirable result of enhanced ESD protection through energy sharing.

Ground 3: Claims 1-18 are obvious over Ker

  • Prior Art Relied Upon: Ker (Patent 6,249,410).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ker discloses a pad circuit with ESD detection circuits 545 and 565 (the "control circuit" and "enable circuitry") that activate an output transistor (e.g., PMOS Mp1) in response to an ESD event. This connects the I/O pad to the Vdd rail, allowing ESD energy to charge the capacitance of other devices on the rail. Ker's voltage clamps 520 and 570 were mapped to the "clamp device" limitation. Petitioner further argued that a POSITA would find it obvious to use a more advanced ESD detection circuit from Ker's other embodiments (e.g., Fig. 37) as the control block. As with the other grounds, Petitioner asserted a POSITA would have been motivated to replicate Ker's circuit at every I/O pad for comprehensive protection, enabling system-wide energy sharing.
    • Motivation to Combine: Not applicable for this single-reference ground. The motivation was based on the standard industry practice of protecting all I/O pads on an integrated circuit, making the repetition of Ker's protective scheme a predictable design choice.
    • Expectation of Success: Success would be highly expected, as the components were standard and their behavior predictable. Applying the protection circuit universally across all I/O pads was a known and reliable method for improving overall device immunity to ESD events.

4. Key Claim Construction Positions

  • While Petitioner stated that no formal claim constructions are necessary, its arguments for several limitations relied on adopting the Patent Owner's apparent interpretations derived from co-pending district court litigation.
  • For example, Petitioner argued that even under an interpretation where the "first voltage rail" and "second voltage rail" can be the same rail, the prior art still discloses the claimed features. This strategy was employed to demonstrate unpatentability regardless of the construction ultimately adopted by the Board.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-18 of Patent 7,564,665 as unpatentable.