Micron Technology Inc v. Yangtze Memory Technologies Co Ltd

1. Case Identification

• Case #: IPR2024-00909
• Patent #: 10,658,378
• Filed: May 19, 2024
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Yangtze Memory Technologies Company, Ltd.
• Challenged Claims: 1-7 and 18

2. Patent Overview

• Title: Through Array Contact (TAC) For Three-Dimensional Memory Devices
• Brief Description: The ’378 patent relates to a three-dimensional (3D) NAND memory device featuring "through array contacts" (TACs), which are vertical electrical connections designed to extend through the memory array to connect with peripheral devices located underneath.

3. Grounds for Unpatentability

Ground 1: Obviousness over Toyama - Claims 1-7 and 18 are obvious over Toyama in view of the knowledge of a person of ordinary skill in the art (POSITA).

• Prior Art Relied Upon: Toyama (Application # 2017/0179026).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Toyama, which describes a 3D memory device with "through-memory-level via structures," discloses or renders obvious every limitation of the challenged claims. The petition asserted that Toyama teaches the core components of the claimed 3D NAND device, including a semiconductor substrate, an alternating conductor/dielectric layer stack, channel structures, slit structures, and a staircase structure for word line contacts. Crucially, Petitioner contended that Toyama also discloses the two elements that distinguish the challenged claims from those in a previously filed IPR: an "epitaxial layer" and an "etch stop plug." Petitioner mapped Toyama's "pedestal channel portions 11," which are formed via selective semiconductor deposition, to the claimed epitaxial layer. It further argued that Toyama's "drain regions 63," made of polysilicon and positioned between the memory stack and overlying contacts, would have been understood by a POSITA to function as an etch stop plug, preventing damage to the memory stack during the etching process used to form the contacts. The petition detailed how Toyama’s structures meet the limitations for through array contacts (TACs), a dielectric structure isolating the TACs, and contact layers on the TACs, channel structures, and slit structures.
  • Motivation to Combine (for §103 grounds): The argument centered on a single primary reference, with a POSITA's knowledge providing the rationale for any interpretations or minor modifications. For the "etch stop plug" element, Petitioner argued that a POSITA, knowing that the overlying dielectric layers in Toyama would be etched to form contacts, would understand that the polysilicon "drain regions 63" would inherently and obviously function as an etch stop to protect the underlying memory channel structures. This was presented as a routine and predictable application of well-known semiconductor manufacturing principles (selective etching), not an inventive combination. Similarly, forming Toyama's "pedestal channel portions" as an epitaxial layer was argued to be an obvious design choice to improve memory channel performance, a known benefit of epitaxy.
  • Expectation of Success (for §103 grounds): Petitioner asserted that a POSITA would have had a high expectation of success, as the claimed invention represents a predictable combination of conventional 3D NAND architectural elements and well-understood fabrication techniques, all of which are disclosed or suggested in Toyama.

4. Key Claim Construction Positions

• Petitioner argued that the claim 1 limitation "a staircase structure in the alternating layer" contains a typographical error and should be construed to mean "a staircase structure in the alternating layer stack." Petitioner contended this construction is necessary because the claim lacks an antecedent basis for "the alternating layer" but does recite an "alternating layer stack." The specification's only support for a staircase feature is in the context of the entire stack, further justifying the correction of what Petitioner asserted is an evident error.

5. Arguments Regarding Discretionary Denial

• §314(a) / Fintiv Factors: Petitioner argued against discretionary denial under Fintiv, asserting that factors weigh in favor of institution. It noted that the trial date in the parallel district court litigation is December 1, 2025, well after the statutory deadline for a Final Written Decision (FWD) in the IPR. Petitioner also stated that little substantive progress had been made in the district court case and that it would stipulate not to pursue in district court any invalidity ground raised or that could have been reasonably raised in this petition, thereby eliminating issue overlap.
• §325(d): Petitioner argued that denial under §325(d) would be inappropriate because the U.S. Examiner overlooked the most material teachings of Toyama during prosecution. Petitioner explained that although the Patent Owner cited Toyama in an Information Disclosure Statement (IDS), it failed to provide the Examiner with a corresponding rejection from the Chinese Patent Office for a counterpart application. That Chinese rejection, which was later affirmed on appeal in China, specifically mapped elements of Toyama to claims materially identical to those challenged here, including the key "epitaxial layer" and "etch stop plug" limitations. Petitioner contended that Patent Owner's omission prevented the Examiner from appreciating Toyama's significance, leading to an error that the Board should now correct.

6. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-7 and 18 of the ’378 patent as unpatentable.