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IPR2025-00085

MediaTek Inc v. Redstone Logics LLC

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1. Case Identification

2. Patent Overview

  • Title: Communication Between Processor Cores
  • Brief Description: The ’339 patent describes techniques for managing communication between sets of processor cores in a multi-core processor. The invention facilitates dynamic and independent control of voltage supplies and clock signals for different sets of cores to optimize power consumption and performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Knoth and Allarey - Claims 1, 5, 8-10, 14, and 21 are obvious over Knoth in view of Allarey.

  • Prior Art Relied Upon: Knoth (Application # 2009/0158078) and Allarey (Patent 8,122,270).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Knoth taught a multi-core processor system with individual cores (110a, 110n) that have independently controlled and dynamically scaled voltage and clock frequencies, managed by respective voltage controllers and clock ratio controllers containing phase-locked loops (PLLs). Knoth also disclosed a coherency manager to facilitate communication between these cores. Petitioner contended that while Knoth depicted individual cores, modifying this to manage "sets" of cores would be an obvious extension, particularly in light of Allarey, which explicitly disclosed managing sets of cores (e.g., "site 0" and "site 1") with independent voltage and frequency domains. The combination, therefore, taught a multi-core processor with a first set and second set of cores, each dynamically receiving independent supply voltages and output clock signals from independent PLLs, and an interface block for communication, as claimed.
    • Motivation to Combine: A POSITA would combine Knoth and Allarey as they addressed the same problem of power management in multi-core processors. Knoth provided a detailed framework for core-level dynamic adjustments, while Allarey provided a method for managing groups of cores and ensuring voltage stability during such adjustments. Combining them would improve overall processor performance and stability by applying Knoth’s dynamic control to Allarey’s more scalable site-level architecture.
    • Expectation of Success: Success was expected because the combination involved applying a known technique (Knoth’s core-level control) to a known system ready for improvement (Allarey’s site-level architecture), representing a mere substitution of known elements to achieve predictable results.

Ground 2: Obviousness over Naffziger and Allarey - Claims 1-3, 5, 8-10, 14, and 21 are obvious over Naffziger in view of Allarey.

  • Prior Art Relied Upon: Naffziger (Application # 2010/0122101) and Allarey (Patent 8,122,270).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Naffziger, like Knoth, disclosed a multi-core processor with cores (105A, 105B) having separate, independent core supply voltage planes and independently controlled clock signals from a power control unit. This power control unit monitored workloads and power consumption to adjust operational states. Naffziger's disclosure of independent control for individual cores, when combined with Allarey's teaching of managing sets of cores ("sites"), rendered the claimed invention obvious. Specifically, Naffziger provided the independent power/clock control architecture, and Allarey provided the motivation and method to apply that control to sets of cores. The combination also taught the use of level shifters (in Naffziger's voltage control unit) to handle differing supply voltages between cores, meeting limitations of dependent claims 2 and 3.
    • Motivation to Combine: A POSITA would combine Naffziger and Allarey to leverage their complementary solutions. Naffziger focused on dynamic power and performance adjustments for individual cores, while Allarey addressed stabilizing supplied voltage during clock frequency changes, particularly in a grouped-core environment. A POSITA would find synergy in combining Naffziger's dynamic adjustments with Allarey's voltage stabilization and grouped-core management to improve overall processor performance and stability.
    • Expectation of Success: The combination involved inter-related, well-known techniques. Integrating Naffziger's power adjustment methods into Allarey's stable, site-based architecture was a predictable path to enhancing performance in a multi-core system.

Ground 3: Obviousness over Knoth, Allarey, and Flautner - Claims 2-4 are obvious over Knoth and Allarey in view of Flautner.

  • Prior Art Relied Upon: Knoth (Application # 2009/0158078), Allarey (Patent 8,122,270), and Flautner (Application # 2005/0034002).
  • Core Argument for this Ground:
    • Prior Art Mapping: Building on the combination of Knoth and Allarey, Petitioner argued that Flautner explicitly taught the interface components required by claims 2-4. Flautner disclosed an interface between two processor cores operating in different voltage and clock domains. This interface included a voltage level shifter (52) to translate signal voltages and a synchronization module (50) to handle different clock speeds. Adding Flautner’s explicit level shifter and synchronizer to the interface block (coherency manager) of the Knoth/Allarey combination would have been obvious to address the known issues of communicating between independently powered and clocked core sets.
    • Motivation to Combine: A POSITA, having combined Knoth and Allarey, would recognize the need for specific components to manage communication across different voltage and clock domains. Flautner directly addressed this need by providing detailed implementations for clock synchronization and voltage level shifting. A POSITA would be motivated to incorporate Flautner's components to ensure reliable communication and improve the robustness of the combined Knoth/Allarey system.
    • Expectation of Success: Success was expected because it involved adding standard, known components (level shifters and synchronizers) to solve a predictable problem (signal integrity between asynchronous domains) in a known system.
  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Wolfe (Application # 2011/0153984) to teach grid-like physical layouts of processor cores and Kumar (Application # 2007/0080696) to teach maintaining specific differential voltage relationships between core sets.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was inappropriate. The co-pending district court case was in its early stages, with trial scheduled for 19 months away, well after the statutory deadline for a Final Written Decision in this IPR. Furthermore, Petitioner noted the merits of the petition are strong, all asserted claims are challenged, and a stay of the district court case is possible if the IPR is instituted.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-6, 8-11, 14, and 21 of the ’339 patent as unpatentable under 35 U.S.C. §103.