PTAB

IPR2025-00118

Micron Technology Inc v. Yangtze Memory Technologies Co Ltd

Key Events

Petition

petition

Title: Integrated Circuit Electrostatic Discharge Bus Structure and Related Method
Brief Description: The ’164 patent relates to an integrated circuit (IC) structure and method designed to make more efficient use of chip area. The invention discloses segmenting an electrostatic discharge (ESD) bus to create empty "saved areas" between pad groups, which can then be utilized for additional circuitry to reduce overall chip size.

Prior Art Relied Upon: Yoshinaga (Japanese Unexamined Patent Application Publication No. JP2006-93598) and Saint (a 2002 textbook titled "IC Mask Design: Essential Layout Techniques").
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Yoshinaga disclosed an IC structure with the key elements of independent claim 6, including a circuit area, a plurality of ESD buses (termed "reference potential lines"), adjacent pad groups, and empty spaces between the buses and pads. Petitioner contended these empty spaces are the claimed "saved area" where no ESD bus or pad exists.
- Motivation to Combine: A person of ordinary skill in the art (POSITA) would be motivated to combine the references to achieve the common goal of shrinking chip size. Yoshinaga teaches improving ESD protection while keeping the chip small, and Saint expressly teaches using "wasted space" between pads for additional circuitry to "get the chip as small as possible." A POSITA would also have found it obvious to use wire bonding, as taught by Saint and other prior art, to connect Yoshinaga's segmented reference lines, as this was a common and well-known interconnection method.
- Expectation of Success: A POSITA would have had a reasonable expectation of success because implementing wire bonding and utilizing empty chip space for circuitry were routine and well-understood techniques in IC design.

Prior Art Relied Upon: Yoshinaga, Saint, and Haralabidis (Patent 9,070,700).
Core Argument for this Ground:
- Prior Art Mapping: This ground builds on Ground 1 by adding Haralabidis to address limitations requiring a "common ESD bus." Petitioner asserted that while Yoshinaga teaches its segmented ESD buses are connected, it does not specify the implementation. Haralabidis discloses connecting segmented ground rails via a "package common ground rail" that runs around the IC, which Petitioner argued is a common ESD bus.
- Motivation to Combine: A POSITA seeking to implement Yoshinaga's design would look to references like Haralabidis for conventional methods to connect the segmented buses. Haralabidis's common ground rail provides a robust, well-known solution for creating a common reference potential, thereby improving the ESD protection scheme, a goal explicitly shared by both Yoshinaga and Haralabidis. The combination represents applying a known technique (Haralabidis's common rail) to an existing design (Yoshinaga) to achieve a predictable result.
- Expectation of Success: Haralabidis described its common ground ring as "Conventional Art," meaning a POSITA would have readily understood how to implement it in Yoshinaga’s design with a high degree of confidence.

Prior Art Relied Upon: Saint and Haralabidis.
Core Argument for this Ground:
- Prior Art Mapping: This ground used the teachings of the Saint textbook as the baseline IC design. Petitioner argued Saint discloses a standard IC layout with a circuit area, segmented ESD buses (e.g., separate VCC/GND buses for different circuit blocks), adjacent pad groups, and the concept of using "saved areas" between pads to shrink the chip. Haralabidis was then introduced to provide the "common ESD bus" recited in the claims.
- Motivation to Combine: A POSITA designing an IC according to Saint's general principles would be motivated to incorporate Haralabidis's "conventional" common ground rail to connect Saint's segmented buses. This combination would achieve improved ESD protection and noise immunity, key considerations addressed in both references. Haralabidis’s teachings on common ground rails are complementary to Saint's teachings on segmented power/ground strategies and ESD protection.
- Expectation of Success: Since Haralabidis's common ground rail was presented as a conventional technique, a POSITA would have had a high expectation of success in applying it to a standard IC layout as described by Saint, requiring only routine modification.

Petitioner argued that discretionary denial under either 35 U.S.C. §314(a) or §325(d) would be inappropriate.
Fintiv Factors (§314(a)): Petitioner contended the factors weigh strongly in favor of institution. The scheduled trial date in the parallel district court litigation (June 15, 2026) is distant, ensuring the IPR would conclude first. Investment in the litigation is minimal, and Petitioner stipulated it would not pursue the same invalidity grounds in district court, eliminating issue overlap.
Same or Substantially Same Prior Art (§325(d)): Petitioner argued denial is improper because none of the asserted prior art references (Yoshinaga, Saint, Haralabidis) were before the Examiner during prosecution. Furthermore, the asserted references directly disclose the "saved area" concept that the Examiner identified as the patent's point of novelty, suggesting the Examiner erred in allowing the claims.

Petitioner requests institution of an inter partes review and cancellation of claims 1-14 of Patent 10,879,164 as unpatentable.