PTAB

IPR2025-00207

Arm Ltd v. DAEDALUS PRIME LLC

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1. Case Identification

2. Patent Overview

  • Title: System and Method for Providing a Common Caching Agent for Microprocessor Cores and an Integrated Input/Output Module
  • Brief Description: The ’228 patent relates to a multiprocessor system architecture designed to improve cache coherency. The patent discloses an apparatus and method using what it describes as a novel "single caching agent" with distributed portions, where each portion is associated with a processor core, to manage cache coherency for both the processor cores and an integrated input/output (IIO) module.

3. Grounds for Unpatentability

Ground 1: Obviousness over Agarwal - Claims 1-2, 4-7, and 11-14 are obvious over Agarwal.

  • Prior Art Relied Upon: Patent 7,805,575 ("Agarwal")
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Agarwal, which is directed to maintaining cache coherence in tiled multicore processors, discloses every element of the challenged claims. Agarwal’s system uses a "Proxy Cache Coherence" (PCC) protocol where the directory controller and directory storage are distributed across multiple "tiles." Petitioner contended that this arrangement of distributed directory controllers, which collectively manage cache coherence for all cores and an integrated I/O module, constitutes the claimed "single caching agent including a plurality of distributed portions." Agarwal’s "tiles" were equated to the claimed "cores," its shared L3 cache to the "shared cache memory," and its I/O module to the claimed "IIO module." For claim 2, Petitioner asserted that Agarwal’s disclosure of a "small buffer" in each tile for outstanding transactions teaches the claimed "table of requests."
    • Expectation of Success: As a single-reference ground, this element is based on the argument that Agarwal inherently teaches or suggests the claimed invention, making it obvious to a Person of Ordinary Skill in the Art (POSITA).
    • Key Aspects: Petitioner emphasized that the PTO had never previously evaluated Agarwal against the ’228 patent or its family. The core of the argument is that the ’228 patent’s supposedly novel architecture is merely a re-characterization of the known distributed directory-based coherence protocol disclosed in Agarwal.

Ground 2: Obviousness over Sinharoy and Combinations - Claims 1-7, 11-14, and 16-19 are obvious over Sinharoy alone or in combination with other art.

  • Sub-Ground 2A: Claims 1, 4, 6, 7, and 11-14 are obvious over Sinharoy.

    • Prior Art Relied Upon: B. Sinharoy et al., “IBM POWER7 Multicore Server Processor,” IBM Journal of Research and Development (2011) ("Sinharoy")
    • Core Argument for this Ground:
      • Prior Art Mapping: Petitioner argued that the IBM POWER7 processor architecture described in Sinharoy discloses the core features of the ’228 patent. Sinharoy’s eight-core processor includes a shared 32-MB L3 cache comprising eight distributed 4-MB regions, with each region incorporated into a corresponding core. The system’s "coherence fabric," comprising distributed L3 cache controllers, was argued to be the claimed "single caching agent with distributed portions." Petitioner asserted that Sinharoy’s integrated I/O controllers and its "cache injection" capability, which allows an I/O device to write directly to the cache, meet the limitations related to the IIO module and its interactions with the caching agent.

  • Sub-Ground 2B: Claims 2, 3, and 16-18 are obvious over Sinharoy in view of Blumrich.

    • Prior Art Relied Upon: Sinharoy; Application # 2011/0219188 ("Blumrich")
    • Core Argument for this Ground:
      • Prior Art Mapping: This ground builds on Sinharoy by adding the teachings of Blumrich to address the "table of requests" limitation in claims 2 and 16. While Sinharoy discloses a "pool of operational resources" for handling requests, Petitioner argued that Blumrich explicitly teaches using a "request queue" to buffer incoming read and write requests for coherence tracking.
      • Motivation to Combine: Petitioner contended a POSITA would be motivated to implement Sinharoy's coherence fabric using Blumrich's request queue. Because Sinharoy’s pool of resources is limited, a POSITA would have recognized the benefit of using a queue, as taught by Blumrich (also an IBM disclosure), to track outstanding requests, prevent overflow, and manage ordering.
      • Expectation of Success: A POSITA would have reasonably expected to succeed in this combination, as it involved applying a known technique (queuing) to improve a known system (a distributed cache controller) to achieve a predictable result.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 5 (requiring a "ring interconnect") is obvious over Sinharoy in view of Sistla (Application # 2008/0126750), which explicitly teaches a ring interconnect for a multicore processor. A further ground combined Sinharoy, Blumrich, and Sistla to argue claim 19 is obvious.

4. Key Technical Contentions (Beyond Claim Construction)

  • "Single Caching Agent" Interpretation: A central technical contention is that the patent's phrase "a single caching agent ... including a plurality of distributed portions" is not a novel structure but rather a functional description of well-known distributed cache coherence systems. Petitioner argued that prior art systems like Sinharoy's POWER7 processor, with its eight distributed L3 cache controllers that collectively form a unified "coherence fabric," meet this limitation. The argument is that although the controllers are physically separate, they operate as a single logical agent from the perspective of the overall system, which is precisely what the ’228 patent describes.

5. Arguments Regarding Discretionary Denial

  • §325(d) and §314(a) (Fintiv): Petitioner argued that discretionary denial would be improper. Under §325(d), Petitioner asserted that the primary references (Agarwal, Sinharoy, Blumrich, Sistla) were never presented to or considered by the examiner during prosecution and are not cumulative of the prior art of record. Under the Fintiv factors, Petitioner argued for institution because: (1) it acted diligently, filing the petition shortly after infringement contentions were served in a parallel district court case; (2) the district court's investment is minimal, with fact discovery and claim construction not scheduled until mid-to-late 2025; (3) there is not a complete overlap of issues, as the IPR challenges claims not asserted in the litigation; and (4) one of the petitioners (Arm Ltd) is not a party to the litigation.

6. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1-7, 11-14, and 16-19 of Patent 8,984,228 as unpatentable under 35 U.S.C. §103.