PTAB

IPR2025-00207

ARM Ltd v. Daedalus Prime LLC

Key Events

Petition

petition

Title: Multiprocessor Cache Coherency
Brief Description: The ’228 patent relates to multiprocessor systems that improve cache coherency management. The disclosed invention is a "single caching agent" with distributed portions, where each portion is associated with a processor core, to handle coherency for both the processor cores and an integrated input/output (IIO) module.

Prior Art Relied Upon: Agarwal (Patent 7,805,575).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Agarwal, which describes a tiled multicore processor architecture, discloses every limitation of the challenged claims. Agarwal’s “Proxy Cache Coherence” (PCC) protocol uses directory controllers and directory storage distributed across processor "tiles." These distributed components collectively manage cache coherence for both CPU and I/O module accesses, functioning as the claimed "single caching agent" with "a plurality of distributed portions." For dependent claims, Agarwal was argued to disclose a "table of requests" (claim 2) via its "small buffer" for outstanding transactions and a last level cache (LLC) with distributed portions (claim 4) via its shared L3 cache distributed across tiles.
- Motivation to Combine (for §103 grounds): As a single-reference ground, the argument focused on Agarwal's direct teachings. Petitioner contended that a person of ordinary skill in the art (POSITA) would have found it obvious to recognize that Agarwal’s distributed directory controllers, which collectively maintain cache coherence, constitute a single, distributed caching agent as claimed.
- Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Agarwal's system already implemented the claimed architecture and functionality.

Prior Art Relied Upon: Sinharoy ("IBM POWER7 Multicore Server Processor," a 2011 journal article).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Sinharoy, which describes the IBM POWER7 processor chip, teaches a system functionally identical to that claimed. The POWER7 processor's distributed "coherence fabric" comprises eight L3 cache controllers that collectively manage a shared 32-MB L3 cache for all cores and integrated I/O modules. This fabric, with its distributed controllers, was argued to be the claimed "single caching agent" with "distributed portions." Sinharoy also allegedly discloses direct-to-cache I/O writes ("cache injection") that do not initiate a memory transaction, meeting the limitations of claims 6, 7, and 11.
- Motivation to Combine (for §103 grounds): This is a single-reference ground. Petitioner argued that Sinharoy's architecture, with its distributed L3 cache controllers acting in concert, would have rendered it obvious to a POSITA to characterize this system as a single caching agent to achieve the known benefits of unified cache management.
- Expectation of Success (for §103 grounds): Success would be expected, as the argument relies on interpreting the inherent operation of the disclosed POWER7 architecture.

Prior Art Relied Upon: Sinharoy (a 2011 IBM journal article) and Blumrich (Application # 2011/0219188).
Core Argument for this Ground:
- Prior Art Mapping: This ground built upon Sinharoy to address claims requiring a "table of requests" (claim 2) and a "dedicated entry to store a posted transaction" (claim 3). Petitioner argued that Sinharoy’s cache controllers have a "pool of operational resources" to handle incoming requests. Blumrich explicitly taught using a "request queue" to buffer and track incoming read and write requests to maintain coherence.
- Motivation to Combine (for §103 grounds): A POSITA would combine Blumrich's request queue with Sinharoy's coherence fabric to efficiently manage the limited operational resources in Sinharoy's controllers. Using a queue to track outstanding requests was a known, common-sense solution to prevent overflow and ensure proper ordering, representing a predictable improvement.
- Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success, as the combination involved implementing a known storage element (a queue) into a known processor architecture (Sinharoy's) to achieve the predictable result of improved request handling.
Additional Grounds: Petitioner asserted additional obviousness challenges, including claim 5 over a Sinharoy-Sistla combination to add a ring interconnect, and claim 19 over a Sinharoy-Blumrich-Sistla combination.

Petitioner argued that discretionary denial under Fintiv is not warranted. The parallel district court trial is scheduled for January 2026, which is after the statutory deadline for a Final Written Decision in this proceeding. Petitioner contended that investment in the parallel litigation is minimal, this petition raises issues and challenges claims (3, 16-19) not present in the litigation, and one petitioner (Arm Ltd) is not a party to the litigation. Finally, Petitioner asserted the merits of the petition are exceptionally strong.

Petitioner requested institution of an inter partes review and cancellation of claims 1-7, 11-14, and 16-19 of the ’228 patent as unpatentable under §103.