PTAB

IPR2025-00212

Phison Electronics Corp v. Vervain LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM
  • Brief Description: The ’298 patent discloses a hybrid non-volatile memory system comprising both Multi-Level Cell (MLC) and Single-Level Cell (SLC) NAND flash memory modules. The system uses a controller to manage data placement between the MLC and SLC modules to improve the operational lifetime (endurance) of the memory system.

3. Grounds for Unpatentability

Ground 1: Obviousness over Gavens - Claims 1-11 are obvious over Gavens in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Gavens (Patent 8,634,240) and its incorporated references, combined with the general knowledge of a Person of Ordinary Skill in the Art (POSITA).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Gavens, a reference from the same portfolio as other prior art cited during prosecution, disclosed a multi-modal NAND flash system capable of operating in both a higher-density (MLC) mode and a lower-density, more robust (SLC-like) mode. Gavens’s controller performs standard address mapping and various error management schemes, including a post-write read that compares written data to a cached original. If errors exceed a threshold (a form of "data integrity test"), the data is remapped to the more robust SLC-like portion. Petitioner asserted that a POSITA would find it obvious to implement Gavens’s lower-density portion using a physically distinct, "real" SLC module for even greater endurance benefits. Gavens also disclosed tracking the "age" of each block via an erase/program count, meeting the limitation of determining which blocks are most frequently accessed.
    • Motivation to Combine: A POSITA, starting with the error-management-focused system of Gavens, would be motivated to incorporate well-known wear-leveling techniques to achieve the common objective of avoiding premature system failure. This would involve not just moving data upon error detection, but also proactively moving frequently written ("hot") blocks, as identified by the access counts Gavens already teaches tracking, to the more durable SLC module.
    • Expectation of Success: Combining known wear-leveling strategies with Gavens's error management system would have been a straightforward application of established principles in NAND flash memory management, leading to the predictable result of improved overall system endurance.

Ground 2: Obviousness over Moshayedi - Claims 1-11 are obvious over Moshayedi in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Moshayedi (Application # 2009/0327591) combined with the general knowledge of a POSITA.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Moshayedi explicitly disclosed a complete hybrid NAND flash system with distinct SLC and MLC modules and a controller performing standard address mapping. Moshayedi is primarily focused on wear-leveling, teaching the controller to track the number of writes to logical blocks or erasures of physical blocks. When a write/erase count for a block exceeds a threshold, Moshayedi's controller allocates that "hot data" by moving or swapping its contents to the more endurant SLC flash. Moshayedi also disclosed tracking data read errors to identify and relocate data from blocks with higher error rates to "blocks with less wear" (i.e., SLC), thereby teaching the claimed "data integrity test" that results in remapping to SLC.
    • Motivation to Combine: The motivation is inherent in Moshayedi's disclosure, which is to prolong the life of the flash memory system. A POSITA reading Moshayedi would understand that its wear-leveling and error-management techniques are complementary methods for achieving the same goal of enhanced reliability and endurance. They would be motivated to use these known techniques together in the disclosed hybrid system.
    • Expectation of Success: A POSITA would have a high expectation of success in implementing Moshayedi's disclosed wear-leveling and error-management functions together, as they were known and compatible strategies for managing hybrid NAND flash systems.

Ground 3: Obviousness over Sutardja - Claims 1-11 are obvious over Sutardja in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Sutardja (Application # 2008/0140918) combined with the general knowledge of a POSITA.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sutardja disclosed a hybrid flash memory system using MLC and SLC modules. Its controller performs wear-leveling by mapping logical addresses with high write frequencies to the SLC memory. Sutardja also disclosed tracking the write/erase counts of physical blocks and remapping data to SLC if a block's wear level exceeds a threshold. Critically, Sutardja taught performing a "degradation test" on physical locations by writing and reading back data over time to assess the block's health. If this test "failed" by showing significant degradation, the system would remap new writes to the more durable SLC memory, which Petitioner argued meets the "data integrity test" limitation.
    • Motivation to Combine: Sutardja's explicit purpose is to avoid premature failure of the memory system. A POSITA would be motivated to use Sutardja’s various disclosed techniques—wear-leveling based on logical address write frequency, physical block wear levels, and degradation testing—in concert to create a robust system that manages endurance comprehensively. Alternatively, a POSITA would be motivated to supplement Sutardja's system with other known error management techniques (such as from Gavens) to further this goal.
    • Expectation of Success: A POSITA would expect Sutardja's disclosed techniques to work together predictably to extend the life of the memory system, as they are all directed to the known problem of managing wear in NAND flash.

4. Key Claim Construction Positions

  • "MLC non-volatile memory module" / "SLC non-volatile memory module": Petitioner argued that a POSITA would understand these terms to mean physically distinct modules with different underlying circuitry, as opposed to different operational modes of a single MLC memory type (e.g., pseudo-SLC). This construction was supported by the patent's language and the established meaning in the art, where "real" SLC memory offers superior endurance over MLC memory operating in a binary mode.
  • "Blocks": Petitioner asserted the term is indefinite as to whether it refers to logical or physical blocks but argued that the claims are obvious under either construction.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv is not warranted. The parallel district court litigation is in a very early stage, with a trial date more than a year away and no claim construction hearing having occurred. Petitioner contended that the IPR is a more efficient forum for resolving the complex technical validity questions, particularly given that eight related patents are asserted in the litigation, and that the petition presents a compelling, meritorious case for unpatentability.

6. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-11 of the ’298 patent as unpatentable under 35 U.S.C. §103.