Kangxi Communications Technologies Shanghai Co Ltd v. Skyworks Solutions Inc

1. Case Identification

• Case #: IPR2025-00372
• Patent #: 9,917,563
• Filed: January 14, 2025
• Petitioner(s): Kangxi Communication Technologies (Shanghai) Co., Ltd.
• Patent Owner(s): Skyworks Solutions, Inc.
• Challenged Claims: 14, 15, 17, and 20

2. Patent Overview

• Title: Apparatus and Methods for Biasing of Power Amplifiers
• Brief Description: The ’563 patent discloses a power amplifier (PA) and a corresponding biasing circuit designed to correct for gain variations that occur at startup due to thermal effects. The invention provides a temporary boost to the PA's bias current when it is first enabled to achieve a flatter, more stable gain response more quickly.

3. Grounds for Unpatentability

Ground 1: Claims 14, 15, 17, and 20 are obvious over Ishimaru in view of Ichitsubo.

• Prior Art Relied Upon: Ishimaru (Application # 2009/0212863) and Ichitsubo (Application # 2004/0232982).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ishimaru discloses a nearly identical architecture to solve the same problem of PA gain variation at startup. Ishimaru teaches a bias circuit with a "speedup circuit" (the claimed "gain correction circuit") that responds to an enable signal by generating a time-varying control current. This control current is then mirrored and amplified by a single transistor (transistor 119) to generate a correction current, which is pulled from a primary biasing circuit to temporarily boost the bias current supplied to the PA. Petitioner asserted this maps to all functional limitations of the challenged claims. Ichitsubo was cited to supply the express teaching of implementing a PA and its associated bias circuitry on a single integrated circuit (IC) attached to a package substrate, forming a "packaged module," which was a routine and well-understood practice.
  • Motivation to Combine (for §103 grounds): A POSITA would combine these references for several reasons. First, it was a routine and expected step to implement a circuit like Ishimaru's, intended for "radio communication devices," in a packaged IC module as taught by Ichitsubo to achieve the well-known benefits of miniaturization, cost reduction, and improved reliability demanded by the market. Second, Ichitsubo itself expressly teaches these benefits for RF PA modules, providing a direct motivation to apply its packaging techniques to Ishimaru's functionally similar circuit.
  • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as packaging a PA and bias circuit on an IC was a routine exercise of skill, not a technologically challenging or counterintuitive step.

Ground 2: Claims 14, 15, 17, and 20 are obvious over Ishimaru in view of Ichitsubo and Harrison.

• Prior Art Relied Upon: Ishimaru (Application # 2009/0212863), Ichitsubo (Application # 2004/0232982), and Harrison (a 2005 book titled "Current Sources and Voltage References").
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented to address a potential claim construction of "current mirror" that requires at least two transistors with tied bases, a configuration not present in Ishimaru's single-transistor mirror. Harrison was introduced to teach a well-known, "basic" two-transistor current mirror that explicitly meets this more restrictive construction. Petitioner argued that a POSITA would replace Ishimaru's single-transistor current mirror (transistor 119) with the conventional two-transistor mirror taught by Harrison. The remaining claim limitations are met by the combination of Ishimaru and Ichitsubo as argued in Ground 1.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Harrison with Ishimaru to improve the circuit's performance. Harrison's two-transistor mirror was known to offer advantages over Ishimaru's simpler single-transistor design, including better linearity, improved isolation between circuit stages, and more predictable, granular gain control by scaling the relative sizes of the transistors. This modification would provide a designer with greater flexibility to adapt the bias correction circuit for different PAs with varying startup characteristics, a predictable improvement yielding known benefits.
  • Expectation of Success (for §103 grounds): Success was predictable because the combination involved substituting one well-understood circuit building block (a single-transistor mirror) with another superior, yet equally well-understood, building block (a two-transistor mirror) to achieve known advantages.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be inappropriate under both 35 U.S.C. §314(a) and §325(d).
• Fintiv Denial: Denial under Fintiv was argued to be inapplicable because the only parallel district court case is stayed, and a parallel ITC investigation is not a basis for Fintiv denial under current USPTO guidance.
• §325(d) Denial: Denial under §325(d) was argued to be improper because the asserted combinations of prior art were never before the examiner during prosecution. While Ishimaru was of record, Petitioner contended the examiner failed to discuss, apply, or otherwise meaningfully address its detailed disclosure, which constituted a material error in allowing the claims.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 14, 15, 17, and 20 of the ’563 patent as unpatentable.