SAP America Inc v. Valtrus Innovations Ltd

1. Case Identification

• Case #: IPR2025-00418
• Patent #: 6,871,264
• Filed: January 14, 2025
• Petitioner(s): SAP America, Inc.
• Patent Owner(s): Valtrus Innovations Ltd. and Key Patent Innovations Ltd.
• Challenged Claims: 1-5 and 8-11

2. Patent Overview

• Title: Dynamically Allocating Cache in a Multi-Processor System
• Brief Description: The ’264 patent relates to a multi-processor integrated circuit capable of executing multiple instruction streams. The system features multiple processors connected via cache controllers and a high-speed interconnect to a plurality of cache memory blocks, allowing for the dynamic allocation of cache resources among the processors.

3. Grounds for Unpatentability

Ground 1: Obviousness over Cherabuddi - Claims 1-3 are obvious over Cherabuddi

• Prior Art Relied Upon: Cherabuddi (Patent 6,725,336).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Cherabuddi’s disclosure of a multi-processor unit (MPU) on a single chip teaches all limitations of independent claim 1. Cherabuddi’s dual CPUs were identified as the claimed first and second processors with their respective cache controllers. Its dynamically partitionable cache memory was mapped to the claimed "plurality of cache memory blocks," and its cache access circuit was argued to function as both the "high-speed interconnect" and the "resource allocation controller." For dependent claims, Petitioner asserted that Cherabuddi's L1 cache within each CPU core meets the "plurality of first level cache systems" of claim 2, and its searchable tag arrays meet the "cache tag memory" of claim 3.

Ground 2: Obviousness over Cherabuddi in view of Dean - Claims 4-5 and 8-10 are obvious over Cherabuddi in view of Dean

• Prior Art Relied Upon: Cherabuddi (Patent 6,725,336) and Dean (Patent 6,604,174).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Cherabuddi provides the base multi-processor architecture with dynamically partitionable cache, as established in Ground 1. Dean was argued to supply the additional limitations found in claims 4 and 5. Specifically, Dean’s system for reallocating cache based on performance metrics was argued to teach a "cache hit rate monitoring apparatus" (claim 4) and the method step of "monitoring past cache performance associated with processors and partitions" (claim 5). The combination was argued to render claims 8-10 obvious as they depend from claim 5 and describe features inherent in or obvious from Cherabuddi's architecture, such as non-allocable cache blocks (private L1 caches) and writeback cache operation.
  • Motivation to Combine: A POSITA would combine the references to improve the performance of Cherabuddi's system. While Cherabuddi teaches dynamically allocating cache based on processing needs, it does not specify a metric for doing so. Dean provides a known, effective metric—cache miss percentage—for guiding this dynamic allocation. A POSITA would therefore be motivated to use Dean's performance-monitoring method to make Cherabuddi's allocation mechanism more intelligent and efficient.
  • Expectation of Success: Success would be expected because the combination involves applying a known performance-monitoring technique (Dean) to a compatible system architecture (Cherabuddi) to achieve the predictable result of improved system performance.

Ground 3: Obviousness over Cherabuddi in view of Noel - Claim 11 is obvious over Cherabuddi in view of Noel

• Prior Art Relied Upon: Cherabuddi (Patent 6,725,336) and Noel (Patent 6,381,682).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the underlying method of repartitioning a system is taught by Cherabuddi. Noel was argued to supply the specific limitations of claim 11, which depends from the method of claim 10. Noel expressly teaches a system that can be repartitioned by "stopping execution of operating systems in each partition, and restarting execution of operating systems in each partition... without rebooting each operating system."
  • Motivation to Combine: A POSITA would be motivated to combine the references to enhance system flexibility and robustness. Cherabuddi discloses dynamic hardware-level cache allocation, while Noel teaches a higher-level, software-based method for managing system partitions without requiring a full reboot. A POSITA would combine these teachings to create a more resilient multi-processor system that could reallocate resources at both the hardware (cache) and software (OS partition) levels on-the-fly to improve resource utilization and avoid system-wide crashes.
  • Expectation of Success: The combination was presented as predictable because both references address partitioning in multi-processor systems and are technically compatible. Applying Noel’s system-level management and rebootless reconfiguration capabilities to Cherabuddi’s underlying cache architecture would be a straightforward integration for a POSITA.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §325(d), emphasizing that the primary reference, Cherabuddi, was never cited or considered by the examiner during the original prosecution.
• Petitioner also argued against discretionary denial under the Fintiv factors (35 U.S.C. §314(a)), asserting that the trial date in a parallel district court litigation is uncertain due to unresolved standing issues that prompted the filing of a second, duplicative lawsuit. Petitioner further contended that the merits of the petition are exceptionally strong and stipulated that, if the IPR is instituted, it will not pursue the same invalidity grounds in the parallel litigation.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-5 and 8-11 of Patent 6,871,264 as unpatentable.