Advanced Micro Devices Inc v. Concurrent Ventures LLC

1. Case Identification

• Case #: IPR2025-00478
• Patent #: 8,924,596
• Filed: March 7, 2025
• Petitioner(s): Advanced Micro Devices, Inc. and Pensando Systems, Inc.
• Patent Owner(s): Concurrent Ventures, LLC and XtreamEdge, Inc.
• Challenged Claims: 1-18

2. Patent Overview

• Title: System for Dividing and Synchronizing a Processing Task Across a Plurality of Processing Elements
• Brief Description: The ’596 patent relates to a system for coordinating access to data queues in a multiprocessor architecture. The patent purports to improve upon prior art software-based synchronization methods (e.g., semaphores) by disclosing a hardware "reservation register" that stores a value indicative of available space in a queue.

3. Grounds for Unpatentability

Ground 1: Obviousness over Dongare and Gewirtz - Claims 1-2, 5-8, 11-14, and 17-18 are obvious over Dongare in view of Gewirtz.

• Prior Art Relied Upon: Dongare (Patent 8,559,439) and Gewirtz (Patent 8,051,227).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Dongare teaches a RAID ASIC architecture comprising a system with multiple processing elements, including a host processor and an embedded processor that manages multiple input and output queues. Dongare provides the overall system architecture but does not detail the specific mechanism for queue management. Gewirtz remedies this by teaching specific techniques for managing queues, including a hardware-based, memory-mapped “Queue State Register” that it also calls a “reservation register.” This register holds the dynamic state of a queue, including the number of free entries, and is accessible by multiple processor cores for flow control purposes.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to improve the performance of Dongare’s system. Dongare’s architecture, with its many queues and variable-rate data flows, creates a clear need for an efficient flow control mechanism. Gewirtz provides a known, simple, and effective solution. A POSITA would combine Gewirtz’s register-based flow control with Dongare’s system to achieve the predictable result of efficient queue management, preventing overflow and improving the overall throughput that Dongare’s multi-engine design seeks to achieve.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination represented a straightforward application of a known solution (Gewirtz’s register) to a known problem (queue management in a multiprocessor system like Dongare’s). Integrating a memory-mapped register for flow control was a routine and well-understood technique in computer architecture.

Ground 2: Obviousness over Khawand and Rosenthal - Claims 1-2, 6-8, 12-14, and 18 are obvious over Khawand in view of Rosenthal.

• Prior Art Relied Upon: Khawand (Patent 7,398,528) and Rosenthal (Patent 5,805,930).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Khawand teaches a multiprocessor architecture where service applications are delegated between processors using queues. Khawand’s “Inter-Processor Manager” evaluates general “flow control criteria,” such as queue capacity, but does not specify the implementation. Rosenthal provides the missing details, teaching a “flow control register” for each FIFO buffer that “stores a value which indicates the amount of space available.” This register is a hardware element accessible by a CPU to determine available space before writing commands, thus preventing overflow.
  • Motivation to Combine: A POSITA would combine these teachings to provide a concrete and efficient hardware implementation for the generalized flow control function required by Khawand’s system. Rosenthal explicitly addresses the fundamental problem of preventing buffer exhaustion in any system using FIFO queues. Applying Rosenthal’s specific register-based solution to Khawand’s architecture is a natural design choice to implement the required flow control, yielding a predictable improvement in system stability and performance.
  • Expectation of Success: Success was expected because combining a specific, well-known flow control mechanism (Rosenthal) with a system architecture that explicitly requires it (Khawand) is a conventional engineering task. The techniques of using hardware FIFOs and control registers were well-established, and their application would predictably improve Khawand’s architecture.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations of these references. Further grounds added Matsunami (Patent 6,810,462) to teach SAN/NAS controller limitations and Ohkawa (Patent 8,028,284) to further teach hardware output queues.

4. Key Claim Construction Positions

• Petitioner argued that the term “[input/output] queue implemented in hardware” should be construed as an “input/output queue implemented in physical circuits without software intervention.” This construction, supported by the patent’s specification, is critical to Petitioner’s argument that the prior art’s disclosure of hardware-based FIFOs and registers directly maps to the claim limitations, distinguishing them from purely software-based queue implementations.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial of the inter partes review (IPR) is not warranted.
  • Fintiv Factors: The parallel district court case is in its earliest stages. Key events like claim construction briefing have not occurred, fact discovery is stayed, and no trial date has been set, weighing in favor of institution.
  • §325(d) Factors (Advanced Bionics): Denial is inappropriate because the core prior art references (Dongare, Gewirtz, Khawand, Ohkawa, Matsunami) and all asserted combinations were not considered during the original prosecution. While Rosenthal was cited in the file history, it was never applied in an office action or rejection. Petitioner contended the Examiner erred by overlooking the material teachings of these references, and this IPR presents art and arguments that are not cumulative.

6. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-18 of Patent 8,924,596 as unpatentable.