PTAB

IPR2025-00501

Yangtze Memory Technologies Co Ltd v. Micron Technology Inc

Key Events

Petition

petition

Title: Semiconductor Devices and Methods of Forming the Same
Brief Description: The ’974 patent relates to three-dimensional (3D) semiconductor memory devices and methods of their manufacture. The disclosed technology focuses on forming vertical memory arrays with through-array vias (TAVs) to connect memory blocks to underlying sub-array circuitry, aiming to reduce the complexity of conventional fabrication processes.

Prior Art Relied Upon: Lee (Application # 2016/0322376).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Lee, which describes a 3D semiconductor device designed to simplify manufacturing, discloses all limitations of the challenged claims. Lee was asserted to teach a memory block coupled to sub-array circuitry (a row decoder) via conductive vias (contact plugs) located in a via region between a memory cell region and a stair step region. Petitioner mapped Lee's "slimming regions" to the claimed stair step regions and its conductive layers to the claimed access lines. For the limitation of "a dielectric material within slots," Petitioner asserted Lee suggests this element, and a person of ordinary skill in the art (POSITA) would find it obvious to fill slots with dielectric material for process isolation, mechanical stability, and preventing electrical crosstalk.
- Key Aspects: This ground asserts that a single prior art reference contains all the key structural and methodological features of the challenged claims, including features the Examiner previously identified as allowable subject matter during prosecution.

Prior Art Relied Upon: Lee (Application # 2016/0322376), Freeman (Application # 2012/0306089).
Core Argument for this Ground:
- Prior Art Mapping: This ground supplements Lee with Freeman to the extent Lee is found not to explicitly disclose specific masking method steps. Dependent claims 12 and 14-19 add limitations requiring the formation of stair step structures by "removing at least a portion" of the structures "using a single stair step mask and two chop masks" or similar mask-based process steps. Petitioner argued that while Lee's figures imply such a process, Freeman explicitly teaches methods for forming nearly identical stair-step structures using a stair-step mask and one or more chop masks to create separate contact regions and reduce device area.
- Motivation to Combine: A POSITA seeking to implement the stair-step structure shown in Lee would combine its teachings with Freeman's explicit and detailed fabrication methods. Petitioner contended the structures in both references are substantially the same, making Freeman's detailed process a natural and obvious supplement to Lee's disclosure to achieve the desired structure with well-known masking techniques.
- Expectation of Success: Given the structural similarities and Freeman's detailed description of a conventional manufacturing process, a POSITA would have had a high expectation of success in applying Freeman's masking techniques to fabricate Lee's device.

Prior Art Relied Upon: Lee (Application # 2016/0322376), Lim (Application # 2016/0163732).
Core Argument for this Ground:
- Prior Art Mapping: This ground addresses dependent claim 13, which recites forming conductive vias by "isolating the conductive vias within the stack of alternating dielectric materials." Petitioner argued that Lee forms its vias through separate "blocking layers," which requires an extra manufacturing step. Lim, in contrast, teaches a "partial gate replacement" process where the vias are formed directly through the remaining alternating dielectric stack, thereby isolating the vias within that stack without needing separate blocking layers.
- Motivation to Combine: A POSITA would combine Lee with Lim to simplify the manufacturing process and reduce costs, consistent with the stated goals of the Lee reference. Lim's partial gate replacement process eliminates the need for the separate blocking layers taught in Lee, reducing process steps while also providing improved mechanical support during fabrication.
- Expectation of Success: Lee and Lim disclose highly similar 3D NAND architectures with under-array circuitry and TAVs. Lim provides explicit guidance on its partial gate replacement process, making it well within the capabilities of a POSITA to apply this known technique to Lee's device to achieve a more efficient manufacturing flow.

Petitioner argued against discretionary denial under 35 U.S.C. §325(d), asserting that the primary references Lee and Lim were never considered by the Examiner during prosecution. While Freeman was cited in an Information Disclosure Statement (IDS), it was never substantively discussed, and Petitioner contended the Examiner overlooked its teachings on the very mask limitations that were deemed allowable.
Petitioner also argued against discretionary denial under 35 U.S.C. §314(a) considering Fintiv factors. It was noted that there is no currently pending parallel litigation, although the Patent Owner recently filed a motion to reassert the ’974 patent in a district court case from which it had been previously withdrawn. Petitioner asserted these "exceptional circumstances" weigh against denial, as minimal investment had been made in the district court case regarding this patent before it was withdrawn.

Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 4, 5, 7, 9, and 11-19 of Patent 10,373,974 as unpatentable.