SanDisk Technologies Inc v. Polaris PowerLED Technologies LLC

1. Case Identification

• Case #: IPR2025-00516
• Patent #: 8,601,346
• Filed: January 23, 2025
• Petitioner(s): SanDisk Technologies, Inc. and Western Digital Technologies, Inc.
• Patent Owner(s): Polaris PowerLED Technologies, LLC
• Challenged Claims: 1-11, 13-18

2. Patent Overview

• Title: Generating Parity Data for a Data Stripe Operation
• Brief Description: The ’346 patent discloses a nonvolatile memory controller for performing data stripe operations. The controller distributes commands across multiple command processing units and uses a parity calculator to generate parity blocks "on the fly" as data is received, thereby reducing the need for large data buffers that store all data blocks simultaneously.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 5-11, 13-16, and 18 are obvious over Jeddeloh, Kleiman, and Ma.

• Prior Art Relied Upon: Jeddeloh (Application # 2011/0078496), Kleiman (Patent 5,950,225), and Ma (Patent 8,341,332).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Jeddeloh disclosed the core architecture of the ’346 patent, including a nonvolatile memory controller with a plurality of "command processing units" (discrete channel memory control circuits) and a "parity calculator" (RAID XOR circuitry) for performing stripe-based memory operations. However, Jeddeloh did not explicitly detail an "on-the-fly" parity calculation. Petitioner asserted that Kleiman, entitled "Fly-by XOR for Generating Parity for Data Gleaned from a Bus," supplied this missing element by teaching a method for performing XOR operations without storing all data blocks in a buffer at the same time. Kleiman’s fly-by XOR element copies data as it is transferred and adds it to an accumulated parity value in an XOR accumulator buffer. Petitioner contended that Ma disclosed the claimed method of data handling, wherein Jeddeloh's command processing units would request data blocks from a host via DMA techniques when ready to process a queued command.
  • Motivation to Combine: A POSITA would combine Kleiman with Jeddeloh to implement Jeddeloh’s generally described RAID XOR circuitry with Kleiman’s well-known and resource-efficient "on-the-fly" technique. This combination would predictably improve performance and reduce buffer requirements. A POSITA would further incorporate Ma's teachings because Jeddeloh explicitly mentions that its switch can be a direct memory access (DMA) module. Ma provided a known technique for implementing DMA operations between a switch and multiple memory controllers, fulfilling Jeddeloh’s suggestion and yielding the predictable result of efficient data transfer from the host.
  • Expectation of Success: Petitioner asserted a high expectation of success because the combination involved applying known techniques to their intended purposes. Kleiman’s on-the-fly parity calculation was a well-established method for RAID systems like Jeddeloh's, and Ma's DMA techniques were directly applicable to the solid-state storage devices described in Jeddeloh.

Ground 2: Claims 4 and 17 are obvious over Jeddeloh, Kleiman, Ma, and Yashiro.

• Prior Art Relied Upon: Jeddeloh (Application # 2011/0078496), Kleiman (Patent 5,950,225), Ma (Patent 8,341,332), and Yashiro (Patent 5,787,460).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds upon the combination of Jeddeloh, Kleiman, and Ma from Ground 1 and adds Yashiro to address the limitations of claims 4 and 17. Petitioner argued that these claims require determining that the parity block generation is complete by using a "stripe count" that reaches a "threshold value." Yashiro disclosed this exact technique, teaching the use of a counter that is incremented for each write operation. When the counter reaches a predetermined threshold, the system recognizes that the parity block is complete and can be stored. This mapped directly to the "stripe count" and "threshold value" limitations.
  • Motivation to Combine: A POSITA implementing the on-the-fly parity calculation of Jeddeloh/Kleiman would require a mechanism to determine when the final data block for a given stripe has been processed. Petitioner argued that using a counter, as taught by Yashiro, was a simple, common, and obvious solution to this problem. The motivation was to implement a tried-and-true technique to achieve a predictable function: accurately determining the completion of the parity calculation.
  • Expectation of Success: Using a counter to track the number of processed data blocks is a fundamental and highly predictable technique. Applying Yashiro’s counter method to the Jeddeloh/Kleiman/Ma system would reliably result in accurately determining when the parity block is complete, with no technical hurdles to overcome.

4. Key Claim Construction Positions

• Petitioner argued that the claim term "without storing each data block in a data buffer" should be construed to mean "without storing each data block in a data buffer at the same time."
• This construction was asserted to be critical because a literal interpretation could be internally inconsistent with claim 1, which recites storing a first data block in a "page frame" (a type of buffer). The proposed construction aligns with the patent’s stated objective of solving the prior art problem of consuming significant area and power by storing all data blocks for a stripe in individual data buffers simultaneously.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under Fintiv, asserting that the factors favored institution.
• Key arguments included that no trial date was scheduled in the parallel district court litigation, and the projected trial date was six months after the statutory deadline for a Final Written Decision. Furthermore, investment in the parallel case was minimal, and the full overlap of issues was speculative. Petitioner also argued that denial under §325(d) was unwarranted because the primary prior art references (Jeddeloh, Kleiman, Ma, and Yashiro) were not before the Examiner during the original prosecution, and thus the petition raised new, compelling arguments of unpatentability.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-11 and 13-18 of the ’346 patent as unpatentable.