PTAB

IPR2025-00517

SanDisk Technologies Inc v. Polaris PowerLED Technologies LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Interrupt Coalescing for Memory Controller
  • Brief Description: The ’968 patent discloses a non-volatile memory controller that communicates with a host processing unit. The core technology involves a technique known as interrupt coalescing, where the controller delays sending interrupt signals to the host—notifying it of unprocessed command completions—until specific configurable conditions, such as a time threshold or a response count, are met.

3. Grounds for Unpatentability

Ground 1: Claims 1-18 are obvious over Borchers

  • Prior Art Relied Upon: Borchers (Application # 2010/0262979).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Borchers teaches all limitations of the challenged claims by describing the same fundamental interrupt coalescing technique. Borchers’ “interrupt processor” was mapped to the claimed “interrupt manager,” and its “response buffer” was mapped to the “completion queue.” Petitioner contended that Borchers’ use of status information—such as an updated response queue head pointer (“ResponseHead”) and the number of outstanding responses—is equivalent to the claimed “completion queue state.” Further, Borchers’ mechanisms for triggering an interrupt, including a “ResponseNew Counter” and a “Last Response Timer,” were argued to be the claimed “interrupt vector state.” The claimed “doorbell update status” was mapped to Borchers’ disclosure of the interrupt processor receiving an indication “when the ResponseHead is updated” by the host.
    • Motivation to Combine (for §103 grounds): This ground was presented as a single-reference obviousness challenge. The motivation to implement certain features, such as using standard interrupt message packets, was based on Borchers’ explicit mention of a PCIe interface, which would lead a person of ordinary skill in the art (POSITA) to incorporate background knowledge of the corresponding industry standards.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success in implementing the claimed features, as Borchers provides a complete blueprint for an interrupt coalescing system.

Ground 2: Claims 1-18 are obvious over Borchers and the PCI Standards

  • Prior Art Relied Upon: Borchers (Application # 2010/0262979) and the PCI Standards (PCI Local Bus Specification 3.0 and PCI Express 2.0 Base Specification Revision 0.9).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground supplements Ground 1 by formally combining Borchers with the PCI/PCIe standards, rather than treating the standards as mere background knowledge. The mapping of Borchers to the claim limitations remained the same as in Ground 1. The PCI standards were used to explicitly teach that modern interrupt signals are implemented as “interrupt message packets” (e.g., Message Signaled Interrupts or MSI/MSI-X) and include an “interrupt vector,” thereby satisfying these specific claim terms.
    • Motivation to Combine (for §103 grounds): A POSITA would combine these references because Borchers explicitly discloses that its memory interface may include a PCIe interface. To ensure interoperability and functionality, a POSITA would naturally and obviously look to the official PCI/PCIe standards to implement the interface and its associated features, like interrupt signaling.
    • Expectation of Success (for §103 grounds): Success would be expected because the combination involved implementing a known device (Borchers’ controller) using industry-standard, well-documented protocols (the PCI standards) to achieve the predictable result of a standards-compliant interface.

Ground 3: Claims 1-18 are obvious over Borchers, the PCI Standards, and Serebrin

  • Prior Art Relied Upon: Borchers (Application # 2010/0262979), the PCI Standards, and Serebrin (Application # 2011/0197003).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative to address the claim limitations requiring a “completion queue state memory” and an “interrupt vector state memory.” While Petitioner argued in other grounds that storing such state information would be obvious, Serebrin was introduced to provide an explicit teaching. Serebrin discloses a device interrupt manager that uses memory, such as caches or registers, to store various forms of interrupt state information.
    • Motivation to Combine (for §103 grounds): A POSITA implementing the interrupt coalescing system of Borchers would understand the need to temporarily store the state information used by the interrupt mechanisms (e.g., counter values, timer status). Serebrin taught a known and common technique of using registers or cache for this exact purpose in an interrupt manager. A POSITA would combine Serebrin’s conventional storage method with Borchers’ system for the predictable purpose of making the system functional.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as the combination merely applied a known technique (storing state information in registers, from Serebrin) to a known system (Borchers’ interrupt processor) to achieve the predictable result of retained state information.

4. Arguments Regarding Discretionary Denial

  • Fintiv Factors: Petitioner argued against discretionary denial under Fintiv, contending that the parallel district court litigation was in its earliest stages. Key factors cited were the absence of a trial date (with a median time-to-trial extending to January 2027, well past the IPR’s statutory deadline), minimal investment in the parallel case, and that the extent of overlapping issues was speculative.
  • Advanced Bionics Factors: Petitioner argued against denial under §325(d), acknowledging that Borchers was cited during prosecution in an Information Disclosure Statement (IDS). However, Petitioner contended that the Examiner materially erred by never discussing or using Borchers in a rejection and by overlooking its clear teachings on interrupt coalescing and doorbell updates. The petition asserted that the PCI standards constitute new, non-cumulative evidence that clarifies Borchers’ disclosure and demonstrates its applicability to the claims.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-18 of Patent 8,554,968 as unpatentable under 35 U.S.C. §103.