Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00576
• Patent #: 7,732,909
• Filed: February 5, 2025
• Petitioner(s): Apple Inc.
• Patent Owner(s): ImberaTek LLC
• Challenged Claims: 1-33

2. Patent Overview

• Title: Method for Embedding a Component in a Base
• Brief Description: The ’909 patent discloses a circuit board structure where at least one microcircuit is embedded within a hole in a baseboard. Key features include conductive patterns on both sides of an insulating layer, conductive material on the sidewalls of the hole for electromagnetic interference (EMI) protection, and electrical contacts formed using copper that contains both electrochemically and chemically deposited copper.

3. Grounds for Unpatentability

Ground 1: Obviousness over Asahi and Dudderar - Claims 1-33 are obvious over Asahi in view of Dudderar.

• Prior Art Relied Upon: Asahi (Patent 6,489,685) and Dudderar (Patent 6,297,551).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Asahi teaches a multi-layered "component built-in module" that discloses nearly all limitations of the challenged claims, including embedding a semiconductor in a hole within an insulating baseboard and forming conductive patterns on both sides. Asahi further teaches using copper for electrical contacts. Petitioner asserted that Dudderar supplies the primary missing element: a grounded "EMI shield metallization" that extends along the inside wall of a cavity housing an integrated circuit, directly corresponding to the ’909 patent’s claimed interference protection.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Asahi's component module with Dudderar's EMI shielding to predictably mitigate known EMI issues associated with densely packed electronic components. The combination would enhance the component’s protection and improve the overall reliability of Asahi’s device.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because both references describe analogous IC packaging technologies. Dudderar already demonstrated the successful implementation of conventional metallization techniques for EMI shielding, making its application to Asahi’s similar structure straightforward.

Ground 2: Obviousness over Hayashi and Eiji - Claims 1-33 are obvious over Hayashi in view of Eiji.

• Prior Art Relied Upon: Hayashi (JP Patent No. 3207174) and Eiji (JP Application # 2002-016327).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Hayashi discloses the core structure of the challenged claims, including a wiring substrate with a semiconductor element built into an insulating layer, effectively creating a multi-layered board with an embedded component. Petitioner argued that Eiji teaches the key missing limitation of a conductive "shielding layer" composed of a copper plating film formed on the inner surface of a through-hole to shield the embedded electronic components from electromagnetic waves.
  • Motivation to Combine: A POSITA would combine Hayashi’s embedded component structure with Eiji’s shielding layer to solve the known problem of susceptibility to external electromagnetic waves. This combination would reduce noise and stabilize the electrical characteristics of the final device, which is a stated goal of Eiji.
  • Expectation of Success: Success was predictable because the combination involved the application of a known technique (Eiji's shielding) to a known device (Hayashi's embedded-component substrate) to achieve a well-understood benefit. The similarity of the electronic modules in both references would ensure a high probability of successful integration.

• Additional Grounds: Petitioner asserted additional obviousness challenges against claims 12-27 based on Asahi alone and Hayashi alone. Further grounds combined Asahi with Joshi (Patent 4,179,802) and Hayashi with Watanabe (WO 00/09623) to address the specific copper deposition limitations, and asserted three-way combinations (Asahi-Dudderar-Joshi and Hayashi-Eiji-Watanabe) against all challenged claims.

4. Key Technical Contentions (Beyond Claim Construction)

• Product-by-Process Claims: Petitioner argued that the claim limitations reciting "electrochemically deposited copper" and "chemically deposited copper" are product-by-process elements that should be given no patentable weight. Petitioner asserted that because the prior art discloses the final copper structure, the method of depositing the copper is irrelevant for determining unpatentability. Even if considered limiting, Petitioner argued the prior art combinations render these process steps obvious.

5. Arguments Regarding Discretionary Denial

• §325(d) Arguments: Petitioner argued that discretionary denial under 35 U.S.C. §325(d) is inappropriate because the asserted prior art references were either not applied during prosecution or are relied upon for subject matter that is materially different from that considered by the Examiner.
• Fintiv Factors: Petitioner argued that the factors from Apple Inc. v. Fintiv, Inc. weigh in favor of institution. The arguments centered on the early stage of a co-pending district court litigation, a pending motion to transfer that could lead to a stay, and the high likelihood that a Final Written Decision (FWD) would issue several months before any potential trial date, thus promoting efficiency.

6. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-33 of Patent 7,732,909 as unpatentable.