Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00581
• Patent #: 8,368,201
• Filed: February 6, 2025
• Petitioner(s): Apple Inc.
• Challenged Claims: 1

2. Patent Overview

• Title: Method for Embedding a Component in a Base
• Brief Description: The ’201 patent discloses an electronic module and a method for embedding semiconductor components within a base, such as a circuit board. The module comprises a baseboard, at least one component embedded within it, a hardened insulating polymer layer on a surface of the baseboard, conductive patterns on the polymer layer, and conductors within the polymer layer to form electrical contacts.

3. Grounds for Unpatentability

Ground 1: Claim 1 is anticipated by or obvious over Hayashi

• Prior Art Relied Upon: Hayashi (JP Patent No. 3207174).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hayashi, which describes a wiring substrate with a built-in electrical element, discloses every limitation of claim 1. Hayashi’s structure consists of laminated insulating sheets, with insulating sheet 6 serving as the "baseboard" containing an opening for an electrical element 4 (the "component"). Insulating sheet 1, located on the second surface of sheet 6, was identified as the "hardened insulating polymer layer," as it is made of a cured thermoset resin. Petitioner mapped Hayashi’s "wiring circuit layer 3" to the "conductive patterns" and its "via hole conductors 2a" to the "conductors" that extend within the polymer layer to connect the component's electrodes ("contact areas") to the conductive patterns.
  • Motivation to Combine (for §103 alternative): For the "against" limitation, Petitioner argued that although Hayashi’s figure shows a small gap, the specification expressly teaches minimizing voids to improve reliability by flowing the resin before curing. A POSITA would have been motivated to implement this teaching to ensure direct contact between the component and the polymer layer, thereby enhancing structural integrity and promoting more secure electrical contact.
  • Expectation of Success: A POSITA would have expected success because Hayashi explicitly teaches the process of flowing resin to minimize gaps, making the outcome of achieving direct contact predictable.

Ground 2: Claim 1 is obvious over Takayama in view of Hayashi

• Prior Art Relied Upon: Takayama (JP Application # 2001-156457), Hayashi (JP Patent No. 3207174).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted Takayama alone anticipates or renders claim 1 obvious by disclosing a multilayer circuit board with an embedded bare chip component. Takayama's insulating layer 41b functions as the baseboard, with the chip 12 embedded within. The overlying insulating layer 41c, made of cured epoxy or polyimide, serves as the hardened polymer layer, upon which wiring conductors 14 (conductive patterns) are formed. Conductors 16 extend through this layer to connect to the chip's terminal pads 12a. The combination with Hayashi was proposed to address the specific material composition of the baseboard.
  • Motivation to Combine: A POSITA would combine Takayama's structure with Hayashi's teaching of using a glass-impregnated epoxy resin. Both references concern embedding components and describe various resin materials. A POSITA would have been motivated to substitute Hayashi's stronger, well-known baseboard material for Takayama’s insulating layer 41b to increase the overall strength and mechanical reliability of the multilayer circuit board, a known goal in the field.
  • Expectation of Success: The combination involved the simple substitution of one known insulating material for another to gain a predictable benefit (increased strength), a routine design choice for a POSITA.

Ground 3: Claim 1 is obvious over McCormack in view of Sakamoto

• Prior Art Relied Upon: McCormack (Application # 2002/0175402), Sakamoto (JP Application # 2001-339165A).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued McCormack discloses all elements, teaching a circuit board with an integrated circuit component 20 embedded in a cavity within a core substrate 12 (the "baseboard"). A dielectric layer (e.g., layer 30) made of cured polymeric compounds is laminated over the component and substrate, serving as the "hardened insulating polymer layer." Patterned metal layers are formed on the dielectric layers, and metal-lined openings (e.g., metal liner 72) act as "conductors" connecting the component pads to the metal layers. Sakamoto was introduced as an alternative or supplementary reference regarding the baseboard material.
  • Motivation to Combine: A POSITA would have been motivated to apply Sakamoto’s teaching of impregnating a core material (like glass cloth) with epoxy resin to McCormack’s core substrate 12. Sakamoto explicitly describes this as a "reinforcing material" to improve strength. A POSITA would have recognized that reinforcing McCormack's core substrate in this manner would make the resulting chip package more durable and less susceptible to failure from mechanical stress, a common design objective.
  • Expectation of Success: The modification represented the predictable use of a known reinforcing technique from Sakamoto in the analogous device of McCormack to achieve the well-understood benefit of enhanced durability.

• Additional Grounds: Petitioner asserted additional anticipation and obviousness challenges against claim 1 based on Takayama alone, McCormack alone, Sakamoto alone, Asahi alone, Sugaya alone, and the combination of Asahi and Sakamoto, relying on similar technology and mapping arguments.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §325(d), asserting that while prior art references Asahi and Sugaya were cited on the face of the ’201 patent, they were never applied in a substantive office action. Petitioner contended the examiner committed material error by overlooking the clear and unambiguous teachings of these references.
• Petitioner also argued against discretionary denial under Fintiv, asserting that the PTAB’s Final Written Decision would likely issue months before any potential trial date in the parallel district court litigation, which remains in its early stages. The compelling merits of the petition were argued to outweigh any potential inefficiencies.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claim 1 of the ’201 patent as unpatentable under 35 U.S.C. §102 and/or §103.