Apple Inc v. ImberaTek LLC

1. Case Identification

• Case #: IPR2025-00583
• Patent #: 11,071,207
• Filed: February 6, 2025
• Petitioner(s): Apple Inc.
• Patent Owner(s): ImberaTek LLC
• Challenged Claims: 1-6

2. Patent Overview

• Title: ELECTRONIC MODULE
• Brief Description: The ’207 patent describes an electronic module that includes one or more components embedded within an installation cavity of an installation base. The technology focuses on the structure of conductive layers and contact bumps used to connect the embedded components.

3. Grounds for Unpatentability

Ground 1: Claims 1-6 are obvious over Nishiuma in view of Shibata

• Prior Art Relied Upon: Nishiuma (Patent 5,616,520) and Shibata (Application # 2002/0149117).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nishiuma disclosed all elements of claim 1 except for the component’s contact zones comprising aluminum. Nishiuma taught a semiconductor package with a component (chip) in a cavity, first and second conductive layers (surface wires and Ni/Au plating), and first and second contact bumps (Au lands and Au balls). The second conductive layer in Nishiuma, comprising plated Nickel (Ni) and Gold (Au), met the limitation requiring at least two layers of different materials. Shibata was cited to cure the remaining deficiency, as it expressly taught using aluminum for the electrode terminals (contact zones) of a semiconductor chip.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Shibata’s teaching of aluminum electrode pads with Nishiuma’s module for several reasons. Petitioner asserted these included the lower cost of aluminum compared to gold, superior physical properties like conductivity, and the commonality of aluminum pads in the industry. The combination was presented as a simple substitution of a known, conventional material to achieve a predictable result.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because bonding gold bumps (as in Nishiuma) to aluminum pads (as in Shibata) was a well-known and conventional technique in semiconductor packaging before the critical date.

Ground 2: Claims 1-2 and 5-6 are obvious over Nakatani in view of Onda and Glick

• Prior Art Relied Upon: Nakatani (Application # 2002/0159242), Onda (Japanese Publication No. 2001-085473), and Glick (Patent 4,068,022).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Nakatani disclosed a conventional electronic module with a component (surface acoustic wave device) in an installation cavity, an insulating layer, and contact zones comprising aluminum. To meet the claim limitations for conductive layers and dual contact bumps, Petitioner combined Nakatani with Onda and Glick. Onda taught using a pair of bumps—one on the component (second contact bump) and one "tower bump" on the circuit board wiring (first contact bump)—to connect a device. Glick taught fabricating conductive layers from multiple materials (e.g., plating a base layer with additional layers like nickel and gold) to improve adherence and reduce cost.
  • Motivation to Combine: A POSITA would combine Onda with Nakatani to improve the reliability and thermal stress resistance of the connection, as Onda’s tower bumps were designed to buffer such stress. A POSITA would further incorporate Glick’s multi-layer plating teachings into the Nakatani-Onda framework to improve the adherence of the wiring to the substrate and reduce costs by minimizing the use of gold, which were known issues in the art.
  • Expectation of Success: Petitioner contended there was a high expectation of success because combining these elements involved applying known techniques to a known system to achieve predictable benefits. The layered conductor structure taught by Glick was complementary to the plated wiring described by Nakatani, making the integration straightforward for a POSITA.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining the Nishiuma-Shibata base with Glick to teach multi-material conductive layers (Ground 1B), and with Parker (Patent 4,912,844) to teach dimensioning the installation cavity to the size of the component (Grounds 1C and 2B).

4. Key Claim Construction Positions

• Petitioner argued for a specific construction of the phrase "at least one of the first conductive-pattern layer and the second conductive-pattern layer comprises at least two layers of at least two different materials" from claim 1.
• Petitioner contended that the phrase "at least one of" followed by "A and B" means the condition must apply to A, or to B, or to both A and B. Therefore, the claim only required one of the two conductive layers to be comprised of at least two different material layers, not necessarily both. This construction was argued to be critical as some prior art combinations disclosed the multi-layer structure in only one of the relevant conductive layers.

5. Arguments Regarding Discretionary Denial

• §325(d) Arguments: Petitioner argued against discretionary denial under §325(d), stating that none of the primary references (Nishiuma, Shibata, Onda, Parker, Glick) were considered by the Examiner during prosecution. While a patent corresponding to Nakatani was listed in an IDS, it was not cited in any rejection or discussed by the Examiner. Petitioner asserted that the invalidity challenges were not the same as or substantially similar to art or arguments previously presented to the USPTO.
• §314(a) (Fintiv) Arguments: Petitioner argued that the Fintiv factors weighed against discretionary denial. Key arguments included that the petition was filed diligently early in the parallel district court litigation, and that the Board’s Final Written Decision (FWD) would likely issue months before the median time-to-trial in the relevant district (WDTX), thus promoting efficiency.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-6 of the ’207 patent as unpatentable under 35 U.S.C. §103.