Tesla Inc v. Intellectual Ventures II LLC

1. Case Identification

• Case #: IPR2025-00638
• Patent #: 8,898,395
• Filed: March 7, 2025
• Petitioner(s): Tesla, Inc.
• Patent Owner(s): Intellectual Ventures II LLC
• Challenged Claims: 1-2, 5, 7-8, and 11

2. Patent Overview

• Title: Managing Memory in a Computer System
• Brief Description: The ’395 patent discloses methods for managing memory consistency in multiprocessor systems that support transactional memory. The invention uses multiple "observed bits" associated with each cache line to track memory accesses by different groups of instructions, allowing these groups to be atomically committed or rolled back to maintain sequential consistency.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 5, 7-8, and 11 are obvious over Moir in view of Martínez.

• Prior Art Relied Upon: Moir (Patent 7,206,903) and Martínez ("Speculative synchronization: programmability and performance for parallel codes," IEEE Micro, Dec. 2003).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Moir taught the core elements of the challenged claims, including a transactional memory system for multiprocessors. Moir disclosed using multiple indicator bits ("load-marking bits") per cache line on a word-granular basis to monitor memory access during the speculative execution of an instruction group ("critical section"). Upon detecting an interfering access from another thread (e.g., an access to a "load-marked" location), Moir taught that the system discards the changes made by the speculatively executed group and re-executes it, which Petitioner equated to the claimed "rolling back." Moir’s disclosure of setting load-marking bits for different words within the same cache line in response to different instruction groups was argued to meet the limitations of setting a "first bit" for a "first group of instructions" and a "second bit" for a "second group of instructions."
  • Motivation to Combine: Petitioner contended that while Moir disclosed the necessity of rolling back a transaction upon detecting an interfering access, it did not specify the precise timing of this rollback relative to servicing the interfering request. Martínez, which also concerned speculative execution in multiprocessors, was argued to remedy this by teaching an efficiency-improving timing mechanism. Martínez disclosed "squashing" (rolling back) a speculative thread immediately upon detecting a conflicting access and before supplying data to the interfering thread. A POSITA would combine Martínez's timing optimization with Moir's transactional memory framework to achieve the predictable result of improved computational efficiency by avoiding wasted cycles that would occur if the interfered-with thread continued execution. A secondary motivation was that Moir suggested using a conventional "coherency mechanism," and Martínez expressly taught a MESI-like protocol, providing a known technique to implement Moir’s system.
  • Expectation of Success: A POSITA would have had a high expectation of success in this combination. Integrating a known timing optimization (from Martínez) into a known transactional memory system (Moir) to achieve a well-understood benefit (avoiding wasted computation) was presented as a straightforward application of known design principles.

4. Key Claim Construction Positions

• "said processing" (claims 1, 2): Petitioner contended this term lacked a clear antecedent basis in the final claim language. Relying on the prosecution history, where the claim language originated from an allowable dependent claim (application claim 35), Petitioner argued that "said processing" should be construed to refer to its antecedent in the precursor claims: "processing said first group and said second group of instructions according to a value of said indicator." This construction clarified that the processor executing the first and second instruction groups is responsible for the "rolling back," which is triggered by an access from an external agent. This interpretation was asserted as critical to applying the prior art combination to the claim limitations involving rollback.

5. Arguments Regarding Discretionary Denial

• §325(d) Denial: Petitioner argued denial under §325(d) was inappropriate because the core prior art references, Moir and Martínez, were not before the Examiner during the original prosecution. Therefore, the petition raised new questions of patentability that had not been previously considered.
• Fintiv Denial: Petitioner contended that discretionary denial under Fintiv was unwarranted. The arguments centered on the early stage of the co-pending district court litigation, noting that investment had been minimal, no claim construction hearing had occurred, and key discovery was not set to begin for many months. Furthermore, the projected trial date in the litigation was after the statutory deadline for the Board’s Final Written Decision (FWD). Petitioner also argued that the overlap of issues was speculative and minimized because the IPR challenged additional claims not asserted in the parallel proceeding.

6. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-2, 5, 7-8, and 11 of the ’395 patent as unpatentable.