Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

1. Case Identification

• Case #: IPR2025-00682
• Patent #: 8,198,686
• Filed: March 28, 2025
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Ltd.
• Patent Owner(s): Advanced Integrated Circuit Process LLC
• Challenged Claims: 1-35

2. Patent Overview

• Title: SEMICONDUCTOR DEVICE
• Brief Description: The ’686 patent describes semiconductor devices comprising complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The technology involves using different gate structures, including distinct metal gate electrodes and high-k gate insulating films, for n-type and p-type transistors to optimize performance, and incorporates strained silicon technology such as silicon-germanium (SiGe) stressors to enhance carrier mobility.

3. Grounds for Unpatentability

Ground 1: Obviousness over Aoyama - Claims 11-15, 18-22, and 19-22 are obvious over Aoyama

• Prior Art Relied Upon: Aoyama (Application # 2007/0215950).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Aoyama’s third embodiment discloses a complete basis for the challenged claims. It teaches a complementary metal-oxide-semiconductor (CMOS) device with a first MIS transistor (NMOSFET) and a second MIS transistor (PMOSFET). Aoyama’s NMOSFET includes a gate electrode with a second metal film (TaCN), while its PMOSFET includes a gate electrode with a different first metal film (TiN) and a conductive silicide layer. Both transistors use an identical high-k gate insulating film (hafnium silicon oxynitride), are formed with sidewall spacers, and are covered by a silicon nitride etch-stop layer that is planarized to not cover the top of the gate electrodes, thereby mapping to the limitations of independent claims 11 and 19.
  • Motivation to Combine (for §103 grounds): As a single-reference ground, the motivation was inherent to Aoyama’s own disclosure, which teaches the claimed combination of features to solve issues related to gate resistance and work function tuning in advanced CMOS devices.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Aoyama provides a detailed, enabling disclosure for manufacturing the described device.

Ground 2: Obviousness over Aoyama and Hsu823 - Claims 1-3, 5-10, 16-17, 23-28, and 30-35 are obvious over Aoyama in view of Hsu823

• Prior Art Relied Upon: Aoyama (Application # 2007/0215950) and Hsu823 (Application # 2007/0235823).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Aoyama discloses the base structure of the NMOS and PMOS transistors as detailed in Ground 1. Hsu823 was introduced for its teaching of incorporating epitaxial SiGe stressors in the source/drain regions of a PMOSFET. This combination addresses limitations in independent claims 1 and 25 related to strained silicon, specifically forming a "silicon mixed crystal layer" (SiGe) in trenches in the second active region (PMOSFET) to cause compressive stress in the channel. Hsu823 further teaches that a silicon nitride film (CESL) can be used to apply tensile stress to the NMOSFET channel, addressing limitations related to a "second stress" in the first active region.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Hsu823’s SiGe stressors with Aoyama’s PMOSFET to improve device performance. It was well-known and standard industry practice that SiGe stressors increased hole mobility, thereby boosting drive current and operating speed.
  • Expectation of Success (for §103 grounds): A POSITA would have reasonably expected success because integrating epitaxial SiGe was a widely used and predictable method for inducing compressive stress in PMOSFETs to enhance performance.

Ground 3: Obviousness over Akasaka and Hsu823 - Claims 1-4, 6-10, 23-29, 31, and 33-35 are obvious over Akasaka in view of Hsu823

• Prior Art Relied Upon: Akasaka (Application # 2007/0066077) and Hsu823 (Application # 2007/0235823).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Akasaka provides an alternative but analogous base CMOS structure to Aoyama, disclosing NMOS and PMOS transistors with different metal gate electrodes, high-k gate dielectrics (HfSiₓOᵧ), and a silicon nitride etch-stop film. The combination with Hsu823 follows the same logic as in Ground 2: a POSITA would integrate Hsu823’s teachings on SiGe stressors into Akasaka’s PMOSFET to achieve the known benefit of enhanced performance. Additionally, Petitioner argued a POSITA would be motivated to modify Akasaka’s conventional sidewall spacers by incorporating Hsu823’s L-shaped spacer liners and removing the outer spacer to improve gap-filling between dense features, reduce voiding, and enhance stress transfer from the etch-stop layer.
  • Motivation to Combine (for §103 grounds): The motivation was to improve the performance of Akasaka’s device using known, predictable techniques for strain engineering (from Hsu823) and to solve known integration problems like gap-filling in scaled devices (also from Hsu823).
  • Expectation of Success (for §103 grounds): Success was expected because the combination involved applying standard, well-understood process modules (epitaxial SiGe, L-shaped spacers) to a conventional CMOS architecture to achieve predictable improvements.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Aoyama with Hobbs (Patent 6,171,910) to teach using different gate insulating films for NMOS and PMOS devices, and parallel grounds using Akasaka as the primary reference in place of Aoyama.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §325(d) is not warranted. Although Aoyama was cited during prosecution, the Examiner only considered Aoyama’s first embodiment. This petition’s primary grounds rely on Aoyama’s distinct third embodiment, which Petitioner contended anticipates or renders obvious the claims and was materially overlooked by the Examiner. The remaining grounds rely on prior art (Akasaka, Hsu823, Hobbs) never considered by the Examiner.
• To address potential denial under 35 U.S.C. §314(a) and the Fintiv factors, Petitioner stipulated that if IPR is instituted, it will not pursue in the related district court litigation any invalidity ground that was raised or reasonably could have been raised in the IPR.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-35 of the ’686 patent as unpatentable.