PTAB

IPR2025-00828

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

Key Events

Petition

petition

Title: Semiconductor Device
Brief Description: The ’227 patent relates to techniques for improving the performance and reliability of a metal insulator semiconductor field-effect transistor (MISFET). The invention achieves this by extending a high-k gate insulating film from beneath the gate electrode to beneath an adjacent sidewall, while ensuring the film is thicker under the gate electrode than it is under the sidewall.

Prior Art Relied Upon: Matsumoto (Application # 2003/0025135).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Matsumoto's first and fourth embodiments render claims 1-3 obvious. Matsumoto was asserted to disclose a MISFET with a multi-layer insulating sidewall structure comprising a "first insulating sidewall" and a "second insulating sidewall" on each side of the gate electrode. Petitioner contended that both the figures and the described fabrication process in Matsumoto show a continuous high-k gate insulating film extending from under the gate electrode to under at least the first insulating sidewall. Crucially, this film is shown to be thinner under the first sidewall than under the gate electrode due to an etching step. Matsumoto's fourth embodiment was argued to meet claim 2, as the film does not extend under the second sidewall. The first embodiment was argued to meet claim 3, as the film extends under both sidewalls with the same thickness.

Prior Art Relied Upon: Matsumoto (Application # 2003/0025135) and Wang (Application # 2006/0131672).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that while Matsumoto provides the base structure of claim 1, it does not expressly disclose the "buffer insulating film" between the substrate and the high-k film (claims 7-8) or specify that the high-k film is a "Hf based oxide" (claim 14). Wang was introduced to supply these elements, as it teaches a composite gate dielectric including a hafnium-based (Hf) high-k layer formed on an underlying dielectric buffer layer (e.g., silicon oxide or silicon oxynitride).
- Motivation to Combine: A POSITA would combine Wang’s buffer layer with Matsumoto’s device to address the well-known problem of undesirable interfacial reactions between high-k dielectrics and the silicon substrate. Wang explicitly taught that this combination improves carrier mobility and device reliability, directly aligning with the goals of a device designer.
- Expectation of Success: Petitioner asserted a high expectation of success, as combining a buffer layer with a high-k dielectric was a common and predictable technique, and both references employed conventional semiconductor fabrication methods.

Prior Art Relied Upon: Kajiyama (JP Application # 2003-258241).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Kajiyama's first embodiment field-effect transistor anticipates every element of claims 1 and 2. Kajiyama was argued to disclose a high-k gate insulating film on an active region, a gate electrode, and a dual-sidewall structure. Petitioner mapped Kajiyama's fabrication steps, which involve etching the high-k film after forming the gate electrode, to show the resulting film is thinner in the regions where the sidewalls are subsequently formed. The process further describes etching the high-k film from outside the first sidewall before the second sidewall is formed. This results in a final structure where the high-k film extends under the first sidewall but not the second, has a smaller thickness under the first sidewall than under the gate, and is continuously formed, allegedly meeting all limitations of claims 1 and 2.
Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Matsumoto with Mutou (for a buffer film) and Ono (for notched film ends and Hf-based oxide), a standalone obviousness challenge to claims 9 and 14 over Kajiyama, and a combination of Kajiyama with Ono (for notched film ends).

Petitioner argued against discretionary denial under 35 U.S.C. §314(a) by stipulating, pursuant to the Sotera decision, that it will not pursue in co-pending district court litigation any ground that it raised or reasonably could have raised in the IPR, should the petition be instituted.
Petitioner further argued against denial under 35 U.S.C. §325(d), asserting that the primary prior art references, Matsumoto and Kajiyama, were never substantively considered or applied by the Examiner during prosecution. Petitioner contended that it presents a compelling case of unpatentability based on evidence and arguments the Patent Office has not previously evaluated.

Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 6-9, and 14 of Patent 7,579,227 as unpatentable.