PTAB

IPR2025-00831

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with Extended High-k Gate Insulating Film
  • Brief Description: The ’076 patent relates to a metal insulator semiconductor field-effect transistor (MISFET) device. The invention purports to improve driving power and reliability by extending a high-dielectric-constant (high-k) gate insulating film beyond the gate electrode to lie underneath the insulating sidewalls.

3. Grounds for Unpatentability

Ground 1: Claims 1-3 and 7-13 are obvious over Kamata

  • Prior Art Relied Upon: Kamata (Application # 2002/0063299).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that various embodiments in Kamata disclose all limitations of the challenged claims. Specifically, Kamata allegedly teaches a semiconductor device with a high-k gate insulating film (disclosing hafnium, Hf, as an option) formed on a substrate, a gate electrode, and a multi-layer insulating sidewall. The petition asserted that Kamata's figures clearly show the gate insulating film extending laterally beyond the gate electrode but terminating inward of the sidewall's outer edge, thus being "retracted." Kamata was also argued to teach the features of dependent claims, including a silicon oxide buffer layer (claim 2), a Hf-based oxide film (claim 3), a double-layer (claim 8) and triple-layer (claim 9) sidewall, and a tapered end surface on the gate insulating film (claims 11-12).

Ground 2: Claims 1-3, 7-8, and 10-13 are obvious over Guha

  • Prior Art Relied Upon: Guha (Application # 2006/0091432).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Guha's device meets all limitations of independent claim 1 and several dependent claims. Guha discloses a high-k gate insulating film (e.g., hafnium silicate) on a substrate, with a gate electrode formed thereon. The insulating sidewall limitation is allegedly met by Guha's gate spacers and isolating spacers. Petitioner argued Guha's figures show the gate insulating film extending wider than the gate electrode and terminating under the gate spacers, thus being retracted from the outer edge of the full sidewall structure. Guha was also argued to disclose a silicon oxide buffer layer (claim 2), a Hf-based oxide for the gate insulating film (claim 3), and a double-layer sidewall structure (claim 8). The rounded end of Guha's dielectric layer was argued to be "tapered" (claims 11-12).

Ground 3: Claims 1-3, 7-10, and 13 are obvious over Matsumoto in view of Yu

  • Prior Art Relied Upon: Matsumoto (Application # 2003/0025135) and Yu (Patent 6,504,214).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Matsumoto teaches the core structure of claim 1, including a gate insulating film that extends under a multi-layer sidewall structure and is retracted from the sidewall's outer edge. However, Matsumoto does not explicitly teach using a hafnium-based oxide. Yu was cited to supply this limitation, as it teaches using high-k materials like hafnium oxide (HfO2) for the gate dielectric. Furthermore, Yu was used to teach the buffer insulating film of claim 2, disclosing a thin silicon oxide interface layer between the substrate and the high-k dielectric to improve device performance.
    • Motivation to Combine: A POSITA would combine these references because they address related problems in semiconductor fabrication. A POSITA would have been motivated to use Yu’s taught HfO2 in Matsumoto’s device to achieve known benefits, such as superior thermal stability. A POSITA would also have been motivated to integrate Yu’s buffer interface into Matsumoto’s device to achieve Yu's stated goals of reducing atom diffusion and improving channel mobility, which aligns with Matsumoto’s objective of reducing device malfunctions.
    • Expectation of Success: The combination involved applying a known, superior material (Yu's HfO2) and a known structural improvement (Yu's buffer layer) to a conventional transistor structure (Matsumoto) to achieve predictable benefits. The fabrication techniques were well-established, leading to a high expectation of success.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Kamata or Guha with Koyama (Application # 2002/0063299) to teach a HfSiON film, and with Sim (a 2005 journal article) to teach a specific film thickness. Another ground combined Guha with Ahmed (Patent 6,911,695) to teach a specific triple-layer sidewall structure. Further grounds combined Matsumoto with other references, such as Ono (Application # 2005/0051856) to teach a "notched" or curved film end.

4. Arguments Regarding Discretionary Denial

  • §314(a) (Fintiv): To simplify the Fintiv analysis, Petitioner stipulated that if the IPR is instituted, it will not pursue in the related district court proceeding any ground that it raised or reasonably could have raised in the IPR.
  • §325(d) (Advanced Bionics): Petitioner argued that discretionary denial under §325(d) is inappropriate because the primary references asserted in the petition were not applied by the Examiner during prosecution. While different publications by the same inventors may have been submitted in an IDS, Petitioner argued they were not evaluated by the Examiner. Petitioner contended that the petition presents a compelling case of unpatentability based on evidence never considered by the Office, which erred in allowing the claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-13 of the ’076 patent as unpatentable.