PTAB

IPR2025-00847

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Metal Oxide Semiconductor Transistor
  • Brief Description: The ’847 patent discloses a Metal Oxide Semiconductor (MOS) transistor structure featuring raised epitaxial layers next to the gate to form source/drain regions. A key aspect is a spacer formed on the gate sidewall that extends laterally over a portion of these raised epitaxial layers.

3. Grounds for Unpatentability

Ground 1: Obviousness/Anticipation over Lan - Claims 1, 3-9, and 11 are anticipated by or obvious over Lan.

  • Prior Art Relied Upon: Lan (Patent 7,935,590).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lan discloses every limitation of claim 1. Lan teaches a MOS transistor with gates (904, 906) on a substrate (902). It forms epitaxial layers (1006, 1008) in recesses next to the gates, which Petitioner contended would be understood by a Person of Ordinary Skill in the Art (POSITA) to be raised above the substrate surface, a common feature for improving strain transfer. Lan then forms main spacers (1202, 1204) that extend laterally onto a portion of these raised epitaxial layers. Finally, Lan discloses doped source/drain extension areas (1102, 1104) formed in the substrate. Petitioner asserted that Lan also teaches the specific features of dependent claims 3-9 and 11, including PMOS/NMOS types, SiGe/SiC epitaxial materials, multi-layer spacers, non-aligned edges, and lightly doped drains (LDDs).
    • Motivation to Combine (for §103 grounds): Not applicable for anticipation. For obviousness, Petitioner argued that even if Lan’s drawings were not explicit, a POSITA would have found it obvious to form raised epitaxial layers, as this was a well-known technique to improve performance by reducing contact resistance and ensuring adequate strain transfer.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as raised epitaxy was a conventional and predictable technique in strained-silicon technology at the time.

Ground 2: Obviousness over Lan and Liaw - Claim 2 is obvious over Lan in view of Liaw.

  • Prior Art Relied Upon: Lan (Patent 7,935,590) and Liaw (Patent 7,026,689).
  • Core Argument for this Ground:
    • Prior Art Mapping: Claim 2 adds a gate structure comprising a dielectric layer, a conductive layer, and a cap layer. Petitioner argued that Lan discloses a gate with a dielectric layer and a conductive layer that can be either polysilicon or metal. Lan also discloses a cap layer but teaches removing it when using a polysilicon gate to perform a necessary silicidation process. Liaw addresses the "dilemma" of fabricating polysilicon gates with cap layers, which complicates silicidation. Liaw teaches that using a metal gate conductor with a protective insulating cap layer avoids this problem entirely, as silicidation is unnecessary for metal gates.
    • Motivation to Combine (for §103 grounds): A POSITA reading Lan’s disclosure of an optional metal gate would have been motivated to look for ways to optimize its fabrication. Liaw explicitly teaches using a metal gate with a cap layer to solve the precise problems (fabrication complexity, cost, potential for short circuits) associated with the alternative polysilicon process. A POSITA would combine Liaw’s solution with Lan’s metal gate embodiment to achieve predictable benefits, such as simplified manufacturing and improved misalignment tolerance for contacts, without the need for silicidation.
    • Expectation of Success (for §103 grounds): Success was expected because the combination involved applying a known solution (Liaw's cap layer on a metal gate) to a known device (Lan's transistor) to resolve a well-understood fabrication trade-off.

Ground 3: Obviousness/Anticipation over Wang407 - Claims 1 and 3-11 are anticipated by or obvious over Wang407.

  • Prior Art Relied Upon: Wang407 (Patent 7,605,407).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Wang407, which describes forming stressors in MOS devices, discloses all elements of the challenged claims. Wang407 teaches a gate stack (12) on a substrate (2), with raised epitaxial SiGe stressors (32) formed in recesses next to the gate. Petitioner contended that Wang407’s figures and description show these stressors are raised above the substrate surface. Multi-layer spacers (52), comprising a liner oxide and a nitride layer, are formed on the gate sidewalls and extend laterally over the raised epitaxial stressors. Wang407 also discloses LDD regions (50) formed in the substrate outside the epitaxial regions. Petitioner asserted these teachings map directly to the limitations of claim 1 and that Wang407 further discloses the specific PMOS/NMOS structures, SiGe/SiC materials, and L-shaped spacers of the dependent claims.
    • Motivation to Combine (for §103 grounds): Not applicable for anticipation. For obviousness, Petitioner argued a POSITA would have understood Wang407’s teachings and figures to disclose the claimed structure as a standard and expected configuration for strained-silicon transistors.
    • Expectation of Success (for §103 grounds): A POSITA would have expected success in implementing the structure, as all disclosed process steps and components were conventional in advanced semiconductor manufacturing.

  • Additional Grounds: Petitioner asserted additional anticipation and obviousness challenges based on Wang753 and Chen, which also disclose MOS transistors with raised epitaxial layers and specific spacer configurations.

4. Key Claim Construction Positions

  • Petitioner argued that the claim 7 term "an offset spacer, positioned between the gate and the spacer" is potentially indefinite because it seems to require the offset spacer to be both part of, and separate from, the main "spacer."
  • For the purposes of the petition, Petitioner adopted the interpretation it expected the Patent Owner to advance: that a multi-layer spacer satisfies the claim if one of its layers (the "offset spacer") is positioned between the gate and another of its layers (part of the main "spacer").

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, stating that this petition was filed expeditiously, just 27 days after a parallel ITC investigation was instituted and before the ITC had set a schedule or issued substantive orders.
  • Petitioner further contended that the petition is comprehensive, challenging all claims of the ’847 patent, including claims not asserted in any parallel proceeding. Petitioner also asserted the merits of the presented grounds are strong and corroborated by expert testimony.

6. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-11 of the ’847 patent as unpatentable.