PTAB

IPR2025-00848

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method for Fabricating the Same
  • Brief Description: The ’880 patent describes a method for fabricating FinFET semiconductor devices, specifically a method for dividing fin-shaped structures using a single diffusion break (SDB). The key claimed step involves forming an interlayer dielectric (ILD) layer on the SDB structure after the SDB is formed.

3. Grounds for Unpatentability

Ground 1A: Obviousness over Doris and Ha - Claims 1-12

  • Prior Art Relied Upon: Doris (Application # 2017/0054002) and Ha (Application # 2016/0111524).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Doris disclosed a FinFET fabrication method on a silicon-on-insulator (SOI) substrate but expressly taught that the method could be applied to a "bulk silicon" arrangement. Petitioner contended that implementing Doris’s process on a bulk silicon substrate, a well-known alternative, would meet most claim limitations. The key modification required is forming shallow trench isolation (STI) around the fins instead of having a buried oxide layer under them. Ha was cited to show the obviousness of this implementation and its consequences. Specifically, Petitioner argued that the step of etching a trench to cut the fins in Doris's process would inevitably also etch and recess the underlying STI when applied to a bulk silicon substrate, as shown in Ha, thus meeting the limitation of removing part of the gate layer, fin, and STI. Doris was alleged to teach forming the lowest ILD layer after the SDB, satisfying the final limitation of claim 1.
    • Motivation to Combine: A POSITA would be motivated to implement Doris's process on a bulk silicon substrate because Doris itself suggested it, and bulk silicon was a well-known, prevalent, and cost-effective alternative to SOI for FinFETs. A POSITA would combine the teachings of Doris and Ha to understand the obvious consequences of this implementation, namely the necessary formation of STI and its partial removal during the fin-cutting etch step.
    • Expectation of Success: A POSITA would have a high expectation of success because Doris expressly disclosed the modification, and applying known FinFET processes to bulk silicon substrates was a routine and predictable practice.

Ground 2A/2B: Anticipation/Obviousness over Ha - Claims 1-5, 7-8, and 10-11

  • Prior Art Relied Upon: Ha (Application # 2016/0111524).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ha, standing alone, anticipated or rendered obvious the challenged claims, particularly under the Patent Owner's likely broad interpretation of "interlayer dielectric layer." Ha disclosed a complete FinFET fabrication process, including forming fin structures on a substrate surrounded by STI. Ha's process involved forming sacrificial gate patterns over the fins and STI, removing parts of the gates, fins, and STI to form a trench for an SDB, filling that trench with a dielectric to form the SDB, and subsequently forming multiple interlayer insulating layers (e.g., layers 172, 173) over the SDB. Petitioner asserted these steps directly mapped onto the limitations of claim 1.
    • Motivation to Combine (for §103 grounds): Not applicable for anticipation (Ground 2A). For obviousness (Ground 2B), Petitioner argued that to the extent any minor variations were needed to map Ha to the claims, they would have been obvious design choices for a POSITA.
    • Expectation of Success (for §103 grounds): A POSITA would have an expectation of success in implementing Ha's disclosed process, as it was presented as a complete and viable fabrication method.

Ground 2C: Obviousness over Ha and Zhao - Claim 9

  • Prior Art Relied Upon: Ha (Application # 2016/0111524) and Zhao (Patent 9,653,583).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground built upon the teachings of Ha. Claim 9 requires the gate layer to comprise amorphous silicon. While Ha's exemplary embodiment disclosed polysilicon for its sacrificial gate patterns, Petitioner argued it was obvious to substitute amorphous silicon. Zhao was cited for its express teaching that sacrificial gate electrodes in a similar FinFET process could be made of "polysilicon or amorphous silicon."
    • Motivation to Combine: A POSITA would combine Ha and Zhao because both addressed the same technology (FinFET fabrication with SDBs) and faced the same design choices for sacrificial gate materials. Zhao explicitly taught that amorphous silicon was an interchangeable and well-known alternative to polysilicon for this purpose. The motivation was a simple substitution of one known material for another to obtain predictable results.
    • Expectation of Success: A POSITA would have a high expectation of success as amorphous silicon and polysilicon were known to have similar properties and function interchangeably as sacrificial gate materials in FinFET manufacturing.

  • Additional Grounds: Petitioner asserted Ground 1B, which argued claims 1-12 are obvious over Doris and Ha further in view of Colinge (a 2008 textbook), using Colinge as direct prior art rather than just evidence of POSITA knowledge. Petitioner also asserted Ground 2D, arguing claim 12 is obvious over Ha in view of Yu (Application # 2017/0125411) to teach that the dielectric SDB layer comprises silicon oxide.

4. Key Claim Construction Positions

  • Petitioner argued that the term “forming an interlayer dielectric (ILD) layer on the SDB structure” in claim 1 should be construed, in light of the prosecution history, to refer only to the lowest ILD layer formed at the transistor level (i.e., ILD-0). Petitioner contended that the applicant overcame a rejection by distinguishing prior art where the ILD layer was formed before the SDB, and that this distinction would be meaningless if the claim covered any of the multiple upper-level ILD layers that are always formed after the SDB in an integrated circuit. Petitioner presented grounds based on both this narrower construction (Grounds 1A/1B) and the Patent Owner's anticipated broader construction (Grounds 2A-2D).

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. The petition was filed just 27 days after an ITC investigation was instituted, before any schedule was set or substantive orders were issued. Petitioner also noted that no other forum had adjudicated the claims, that the ITC lacks the authority to invalidate claims, and that the merits of the petition were particularly strong. Finally, Petitioner highlighted its significant investments and economic activity in the U.S. as a factor weighing against denial.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-12 of the ’880 patent as unpatentable.