Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

Prosecution History analysis

Examiner Search analysis

Invalidity Framework analysis

Petition

Petition analysis

## 1. Case Identification
- Case Number: [IPR2025-00848](https://ai-lab.exparte.com/case/ptab/IPR2025-00848)
- Patent #: [9,953,880](https://ai-lab.exparte.com/patent/9953880)
- Filed: April 17, 2025
- Petitioner(s): Taiwan Semiconductor Manufacturing Company Ltd., and [Apple Inc.](https://ai-lab.exparte.com/party/apple-inc)
- Patent Owner(s): [Marlin Semiconductor Ltd.](https://ai-lab.exparte.com/party/marlin-semiconductor-ltd)
- Challenged Claims: 1-12

## 2. Patent Overview
- Title: Semiconductor Device and Method for Fabricating the Same
- Brief Description: The [’880 patent](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1001) describes a method for fabricating fin-shaped field-effect transistors (FinFETs) that includes forming a "single diffusion break" (SDB) structure. The SDB is an insulating structure created by etching a trench across the transistor fins and filling it with a dielectric material to electrically isolate adjacent device regions.

## 3. Grounds for Unpatentability

#### Ground 1: Claims 1-12 are obvious over Doris in view of Ha
- **Prior Art Relied Upon:** [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005) (Application # 2017/0054002) and [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) (Application # 2016/0111524).
- **Core Argument for this Ground:**
  - **Prior Art Mapping:** Petitioner argued that [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005) disclosed a FinFET fabrication process that taught nearly all elements of the challenged claims, including forming fins, a gate layer, etching a trench to create an SDB, and filling it with a dielectric. While [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005) primarily illustrated a process on a silicon-on-insulator (SOI) substrate, it expressly stated that the method could be applied to a "bulk silicon ... arrangement." [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) was presented as teaching the conventional modifications needed to adapt [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005)'s SOI process to a bulk silicon substrate. Specifically, [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) taught forming shallow trench isolation (STI) *around* the fins in a bulk silicon process, as opposed to the buried oxide layer *under* the fins in an SOI process. Petitioner contended that when etching the SDB trench in [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005)'s process as applied to a bulk substrate, it would have been obvious to also etch part of the underlying STI, as taught by [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006), thus meeting the limitation of removing part of the STI to form the trench.
  - **Motivation to Combine:** A person of ordinary skill in the art (POSITA) would combine the teachings because [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005) explicitly suggested using a bulk silicon arrangement, a well-known and commercially prevalent alternative to SOI substrates. [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) simply provided the textbook implementation details for this known alternative. The motivation was to achieve predictable results, such as lower wafer cost and different heat transfer properties, by applying a disclosed process to a disclosed alternative substrate.
  - **Expectation of Success:** A POSITA would have a reasonable expectation of success because adapting a FinFET process from an SOI to a bulk silicon substrate was a routine and well-understood modification in the art, involving standard, predictable process steps.

#### Ground 2: Claims 1-5, 7-8, and 10-11 are anticipated by or obvious over Ha
- **Prior Art Relied Upon:** [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) (Application # 2016/0111524).
- **Core Argument for this Ground:**
  - **Prior Art Mapping:** This ground was presented based on the Patent Owner's potential broad interpretation of the claim term "forming an interlayer dielectric (ILD) layer on the SDB structure." Petitioner argued that [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006), by itself, disclosed every limitation of independent claim 1. [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) taught forming fin structures (130) on a substrate with surrounding STI (110), forming a sacrificial gate layer (e.g., gate pattern 75) over the fins and STI, and removing parts of the gate layer, fin, and STI to form a trench (fin active cut-zone CZ3). [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) then disclosed forming a dielectric SDB structure (fin active core 130C) in the trench. Critically, [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) disclosed forming multiple interlayer insulating layers (172 and 173) *after* and *on* the SDB structure. Petitioner contended these layers in [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) met the final limitation of claim 1 under the Patent Owner's broad construction, thereby anticipating the claim.
  - **Motivation to Combine (for §103 grounds):** For the obviousness portion of the argument, the motivation to combine the various steps was contained entirely within [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006)'s own disclosure, which presented them as a single, integrated fabrication process.
  - **Expectation of Success (for §103 grounds):** A POSITA would have an expectation of success in implementing [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006)'s process because [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) presented a complete, coherent method for fabricating FinFET devices.

- **Additional Grounds:** Petitioner asserted additional obviousness challenges, including Ground 1B ([Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005), [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006), and [Colinge](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1007)), which used the [Colinge](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1007) textbook to further evidence the conventional nature of bulk silicon FinFETs. Petitioner also raised Ground 2C ([Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) and [Zhao](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1008)) to render claim 9 obvious by teaching the use of amorphous silicon for the gate layer, and Ground 2D ([Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006) and [Yu](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1009)) to render claim 12 obvious by teaching the use of silicon oxide for the fin active core.

## 4. Key Claim Construction Positions
- **Term:** "forming an interlayer dielectric (ILD) layer on the SDB structure" (claim 1, limitation [1f]).
- **Petitioner's Argument:** Petitioner argued this term must be construed to refer specifically to the *lowest* ILD layer (often called ILD-0), which is formed at the transistor level, directly on the device structures. This construction was based on the patent's prosecution history, where the applicant amended the claim to add this limitation to overcome a rejection based on the [Xie790](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1017) reference. The applicant distinguished [Xie790](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1017) by arguing it formed the ILD layer *before* the SDB, not *after*. Petitioner contended that a POSITA would understand this distinction only applies to the lowest ILD layer, as all integrated circuits necessarily form higher-level ILD layers (for metal interconnects) after the SDB. Construing the term to cover any ILD layer would render the applicant's amendment and arguments during prosecution illusory. The [Doris](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1005)-based grounds were argued to meet this narrower construction, while the [Ha](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1006)-based grounds were presented as an alternative that meets the Patent Owner's allegedly broader construction.

## 5. Arguments Regarding Discretionary Denial
- Petitioner argued that discretionary denial under *Fintiv* would be inappropriate. The petition was filed expeditiously, just 27 days after the institution of a parallel ITC investigation, before any schedule was set or substantive orders were issued in that forum. Petitioner asserted that the merits of the invalidity grounds were particularly strong and that no other forum had yet adjudicated the challenged claims. Furthermore, because the ITC lacks the statutory authority to invalidate patent claims, Petitioner contended that instituting the IPR was necessary to preserve the "efficiency and integrity of the system" and to provide a path to cancellation, an option unavailable in the ITC or the stayed district court litigation.

## 6. Relief Requested
- Petitioner requested institution of an inter partes review and cancellation of claims 1-12 of the [’880 patent](https://ai-lab.exparte.com/docs/ptab/IPR2025-00848/1001) as unpatentable.

Apple & TSMC challenge FinFET patent's 12 claims on obviousness. Doris & Ha cited for single diffusion break (SDB) fabrication on bulk silicon.