PTAB

IPR2025-00879

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: METHOD FOR FABRICATING METAL-OXIDE SEMICONDUCTOR TRANSISTOR
  • Brief Description: The ’473 patent discloses a method for fabricating Metal-Oxide Semiconductor (MOS) transistors. The method involves performing a first photo-etching process to form a gate pattern, forming an epitaxial layer in the substrate adjacent to the gate pattern to induce stress, and then performing a second photo-etching process to cut the gate pattern into two separate gates.

3. Grounds for Unpatentability

Ground 1: Obviousness over Okuno and Shin - Claims 1 and 3 are obvious over Okuno in view of Shin.

  • Prior Art Relied Upon: Okuno (Application # 2009/0309141) and Shin (Application # 2006/0088968).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Okuno taught a method of fabricating MOS transistors that included all steps of claim 1 except for forming an epitaxial layer. Okuno disclosed forming a continuous gate pattern, forming source/drain regions, and then performing a second photo-etching process to cut the gate pattern into separate gates to reduce transistor spacing. Petitioner asserted Shin taught forming recessed source/drain regions and growing an epitaxial layer (SiGe or SiC) within the recesses to introduce compressive or tensile stress, thereby increasing carrier mobility and overcoming short-channel effects. The combination allegedly rendered claim 1 obvious. For claim 3, Okuno was said to disclose forming the gate over shallow trench isolation (STI) regions and removing the gate material over the STI during the gate-cutting step.
    • Motivation to Combine (for §103 grounds): Petitioner contended a POSITA would combine Shin’s epitaxial stressor technique with Okuno’s gate-cutting process to gain the benefits of both: increased transistor density from Okuno and improved device performance (higher drive current, shorter channel length) from Shin. Both references addressed problems related to semiconductor miniaturization.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because adding Shin’s well-known selective epitaxial growth (SEG) process after Okuno's spacer formation and before source/drain implantation was a minor modification using known techniques to achieve predictable results.

Ground 2: Obviousness over Chong and Okuno - Claims 1-10 are obvious over Chong in view of Okuno.

  • Prior Art Relied Upon: Chong (Application # 2008/0142879) and Okuno (Application # 2009/0309141).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Chong disclosed a complete MOS transistor fabrication process including all elements of claim 1 except for the final gate-cutting step. Chong taught forming a gate pattern, hard mask, spacers, lightly doped drains (LDDs), and forming an epitaxial layer (SiGe) in recessed source/drain regions to induce strain. Petitioner asserted that combining Chong’s process with Okuno’s teaching of performing a final photo-etching step to separate a continuous gate pattern into multiple gates would render claims 1-10 obvious. The combination was alleged to disclose the dependent claim limitations, including forming hard masks (Chong’s cap layer), spacers, LDDs, dielectric layers, and specific material compositions like silicon nitride.
    • Motivation to Combine (for §103 grounds): Petitioner argued a POSITA would be motivated to apply Okuno’s gate-cutting technique to Chong’s process to solve miniaturization challenges. Okuno’s method of patterning a continuous gate strip and cutting it last was a known solution to overcome photolithography limits (e.g., line-end shortening) and increase transistor density, which was a goal shared by Chong. Performing the gate separation after all source/drain formation steps, as taught by Okuno, would also prevent asymmetrical impurity implantation in Chong’s device.
    • Expectation of Success (for §103 grounds): Success was expected as gate-cutting was a conventional technique applied to a standard MOS fabrication flow to achieve the predictable result of size reduction. Okuno expressly taught that performing the cut last ensures symmetrical impurity characteristics, providing a clear reason to apply it to Chong's completed source/drain structure.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 1-3 over Mandelman (Application # 2008/0251878) and Shin, and for claims 1-6 over Chong and Mandelman. These grounds relied on similar arguments, substituting Okuno’s gate-cutting disclosure with Mandelman’s, which also taught forming a continuous conductor line and subsequently segmenting it via a second photo-etching step to overcome photolithography issues in densely packed devices.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, stating that a parallel ITC investigation was instituted only 27 days before the IPR petition was filed. At the time of filing, the ITC had not set a schedule or issued any substantive orders, weighing against denial. Petitioner also noted that the IPR challenges every claim of the ’473 patent, including all claims asserted in the ITC, and that no other forum had previously adjudicated the claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’473 patent as unpatentable.