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IPR2025-00954

NXP Semiconductors N V v. Harbor Island Dynamic LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor on Insulator Switching Circuit
  • Brief Description: The ’886 patent relates to a semiconductor on insulator (SOI) switching circuit with cascaded transistors. The purported invention is a transistor structure that includes an intervening portion of a device layer between the source/drain junctions and a buried oxide (BOX) layer, which creates a source/drain junction capacitance similar to that of a conventional bulk silicon transistor.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 4, and 5 are anticipated by Okashita under 35 U.S.C. §102.

  • Prior Art Relied Upon: Okashita (Patent 6,836,172).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Okashita discloses every limitation of the challenged claims. Okashita describes a semiconductor switch apparatus for a mobile telephone with cascaded MOS transistors fabricated in an SOI configuration. Specifically, Petitioner asserted that Okashita’s Figure 9 clearly illustrates an intervening silicon layer separating the source/drain junctions of its transistors from the top surface of a buried silicon oxide layer, which is the core structure claimed in the ’886 patent. Petitioner contended that a person of ordinary skill in the art (POSITA) would have immediately recognized that this structure inherently forms the claimed source/drain junction capacitance. Furthermore, Okashita was argued to disclose isolation trenches extending through the device layer to contact the buried oxide layer, thereby forming the claimed "isolated island" for the transistors.

Ground 2: Claims 1-3 are anticipated by Yu under 35 U.S.C. §102.

  • Prior Art Relied Upon: Yu (Patent 6,737,682).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yu, which discloses a low-voltage triggering, silicon-controlled rectifier (LVT-SCR) for electrostatic discharge protection, also anticipates the key features of claims 1-3. Yu's device is built on an SOI structure and includes two cascaded MOS transistors. Petitioner highlighted that Yu explicitly teaches making the silicon layer "thick enough so that the doped regions do not completely deplete the wells" and do not extend to the buried oxide layer. This teaching was presented as a direct disclosure of the ’886 patent's central feature. Yu also teaches using shallow trench isolation (STI) regions that extend down to the buried insulator layer to "completely isolated" the active area, thereby disclosing the claimed trench and isolated island structure.

Ground 3: Claims 1-19 are obvious over Burgener in view of Okashita under 35 U.S.C. §103.

  • Prior Art Relied Upon: Burgener (Application # 2006/0270367) and Okashita (Patent 6,836,172).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Burgener provides the system-level context for the invention, disclosing an integrated circuit for an RF transceiver in a wireless communication device, such as a cellular phone. Burgener’s circuit includes an antenna switch that uses "stacks of multiple FETs connected in series" (i.e., cascaded transistors). While Burgener does not detail the specific transistor fabrication, it expressly suggests that its circuit may be fabricated using "semiconductor-on-insulator (SOI) techniques." Okashita was presented as teaching the specific SOI transistor structure needed to complete the combination.
    • Motivation to Combine: A POSITA would combine Burgener’s RF switch with Okashita’s specific transistor structure for several predictable benefits. First, Burgener itself suggests using SOI techniques, making Okashita a natural reference to consult. Second, a POSITA would have been motivated to implement Okashita's structure—with its intervening silicon layer between the source/drain and the buried oxide—to improve the thermal performance and reliability of Burgener's FETs, as this structure was known to reduce operating temperatures in SOI devices. Third, a POSITA would use Okashita’s trench isolation to prevent signal leakage between the different stacks of FETs in Burgener’s switch, thereby improving electrical performance.
    • Expectation of Success: Petitioner argued a POSITA would have had a reasonable expectation of success because both references are in the same technical field of SOI switching circuits. The combination represented a straightforward application of a known fabrication technique (Okashita) to improve a known device (Burgener) to achieve predictable results.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1-7 are obvious over Okashita alone (arguing it would be obvious to fabricate additional series transistors with the same structure) and that claims 1-7 are obvious over Okashita in view of Yu. A final ground argued that claims 1-19 are obvious over the three-way combination of Burgener, Okashita, and Yu.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-19 of Patent 7,745,886 as unpatentable.