PTAB

IPR2025-00993

Samsung Electronics Co Ltd v. W&Wsens Devices Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Integrated Photodetector Structure
  • Brief Description: The ’871 patent discloses an integrated structure for a photodetector that uses an array of pillars with microstructured holes to enhance light absorption. The structure is configured to be monolithically integrated with control circuitry on a single semiconductor substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kuboi - Claims 1-4, 6-8, and 10-18 are obvious over Kuboi.

  • Prior Art Relied Upon: Kuboi (Application # 2012/0049044).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kuboi, which discloses a CMOS imaging device, teaches all limitations of the challenged claims. Kuboi's device includes a pixel region on a semiconductor substrate comprising a two-dimensional array of pixels (the claimed "array of pillars"), with each pixel functioning as a photodetector. These pillars are made of silicon and have P-doped (p+ region 18) and N-doped (n+ region 17) regions with an intermediate n-type region 16 therebetween. Kuboi further discloses deliberately forming holes (trenches 38) in the light-receiving surfaces of the pillars by dry-etching and filling them with a solid dielectric material (an insulating electron blocking film and an organic photoelectric conversion film). Petitioner contended that Kuboi’s disclosure of using organic materials (porphyrin, phthalocyanine) with absorption coefficients at least ten times larger than silicon inherently satisfies the limitation of increasing light absorption by at least 1.1x over a device lacking holes. This assertion was supported by calculations based on the Lambert-Beer expression and arguments that the Patent Owner’s own statements in the ’871 patent regarding High Contrast Grating (HCG) effects would apply to Kuboi's disclosed structure. Kuboi also discloses monolithic integration of the pixel array with peripheral CMOS logic circuits on a single silicon substrate.
    • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
    • Expectation of Success (for §103 grounds): Not applicable.

Ground 2: Obviousness over Kuboi in view of Shinohara - Claims 1-4, 6-8, 10-16, and 18 are obvious over Kuboi in view of Shinohara.

  • Prior Art Relied Upon: Kuboi (Application # 2012/0049044) and Shinohara (Application # 2012/0033119).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Kuboi taught nearly all elements of the challenged claims, as outlined in Ground 1. To the extent Kuboi's method of bonding a substrate with pixels to a separate substrate with circuitry is not considered "monolithic integration," Petitioner argued Shinohara supplied this teaching. Shinohara explicitly discloses forming a pixel region, peripheral circuit portion, pixel transistors, and wiring layer on the same single substrate.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Shinohara's teaching of monolithic integration with Kuboi’s photodetector design. Kuboi’s method of bonding two separate substrates is more complex and costly than Shinohara’s single-substrate approach. A POSITA would have been motivated to adopt Shinohara’s well-known technique to improve Kuboi's device by reducing manufacturing costs, decreasing package size, and reducing signal noise and attenuation.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as combining these elements involved applying a known manufacturing technique (monolithic integration) to a similar device (a CMOS image sensor) to achieve predictable benefits.

Ground 3: Obviousness over Yu in view of Kuboi and Shinohara - Claims 1-4, 7-8, 15, 17, and 18 are obvious over Yu in view of Kuboi and Shinohara.

  • Prior Art Relied Upon: Yu (Application # 2012/0153124), Kuboi (Application # 2012/0049044), and Shinohara (Application # 2012/0033119).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yu serves as the primary reference, disclosing an image sensor with an array of pixels (the claimed "pillars"), where each pixel contains multiple nanopillars. Yu's pixels are photodetectors made of silicon, include P-doped and N-doped regions, and have deliberately etched holes between the nanopillars that are filled with a solid dielectric (silicon oxide). The deep-etch process described in Yu creates elongated, crisscrossing trenches. Kuboi was cited for its teaching of applying a reverse bias to its photodetectors to decrease response time and induce carrier multiplication. Shinohara was cited again for its clear teaching of monolithic integration of the image sensor and control circuitry on a single chip.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Kuboi's reverse-biasing technique with Yu's image sensor to improve its performance, specifically by increasing response speed. Further, a POSITA would implement the combined Yu-Kuboi structure using Shinohara’s monolithic integration method to gain the known manufacturing and performance advantages over multi-substrate designs.
    • Expectation of Success (for §103 grounds): The combination involved implementing known techniques (reverse biasing, monolithic integration) in a predictable manner to enhance a standard image sensor architecture, leading to a high expectation of success.

4. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-4, 6-8, and 10-18 of the ’871 patent as unpatentable.