PTAB

IPR2025-00996

Samsung Electronics Co Ltd v. W&Wsens Devices Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Single-Chip Device with Microstructure-Enhanced Photodetector
  • Brief Description: The ’700 patent discloses a single-chip semiconductor device that monolithically integrates a microstructure-enhanced photodetector (MSPD) with an active electronic circuit, such as CMOS signal processing circuitry, on a single substrate. The MSPD features intentionally formed holes extending through its layers to enhance light absorption and quantum efficiency.

3. Grounds for Unpatentability

Ground 1: Claims 1-4, 7, 9-12, 16-17, 20-21, 24-26, 28-30, 32, and 35 are Anticipated by or Obvious over Kuboi

  • Prior Art Relied Upon: Kuboi (Application # 2012/0049044).

  • Core Argument for this Ground: Petitioner argued that Kuboi, a reference not considered during prosecution, discloses every element of the challenged claims, rendering them unpatentable under 35 U.S.C. §102 (Anticipation) and/or 35 U.S.C. §103 (Obviousness). The petition presented the obviousness arguments as an alternative, asserting that even if Kuboi does not explicitly disclose certain minor features, a person of ordinary skill in the art (POSITA) would have found it obvious to modify Kuboi’s device to include them.

    • Prior Art Mapping: Petitioner contended that Kuboi’s disclosure of a CMOS solid-state imaging device (201) directly maps to the limitations of independent claim 1.

      • Single-Chip Device: Kuboi’s imaging device 201 was described as a single-chip device comprising a pixel region and a peripheral circuit portion formed on a single semiconductor substrate (211).
      • MSPD and Active Circuit: Kuboi’s photoelectric conversion portion (14), which features etched holes (38) to enhance performance, was identified as the claimed MSPD. The peripheral circuit portion, which includes logic circuits (204-208) for processing pixel signals, was identified as the claimed "active electronic circuit."
      • Layered Structure: The MSPD’s required layers—a first layer (p+-type region 18), an intermediate layer (n-type region 16), and a second layer (n+-type region 17)—were all asserted to be disclosed in Kuboi’s stacked PiN structure.
      • Reverse-Bias Operation: Kuboi’s upper electrode (22) and lower electrode (23) were described as being configured for reverse-bias operation to create a depletion layer and sweep electrical charges, meeting this limitation.
      • Electrodes Free of Matching Openings: Petitioner argued that Kuboi’s transparent upper electrode (22) has no openings, and the openings in the lower electrode (23) for conductors do not align with the pattern of the etched holes (38) in the photodetector, thus satisfying the claim element that the electrodes are "free of a pattern of openings that matches said holes."
      • Signal Processing: The peripheral logic circuits in Kuboi were shown to perform amplification, noise removal, and routing of the electrical output from the MSPD, fulfilling the claim’s processing requirements.

    • Motivation to Combine (for §103 grounds): For certain dependent claims, Petitioner provided obviousness rationales.

      • For claim 2 (circuit extends beyond the substrate), Petitioner argued a POSITA would have been motivated to use conventional and well-known "above-wafer" metal interconnects to wire the transistors of Kuboi’s logic circuits. This standard CMOS fabrication technique would improve reliability and was already suggested in Kuboi, which discloses a multilayer wiring layer (32).
      • For claim 25 (ohmic contact through a via), Petitioner argued that fabricating Kuboi’s pixel transistors on the same substrate as the photodetector was an obvious modification to increase manufacturing yield by avoiding difficult substrate-bonding alignment. In this configuration, a POSITA would have been motivated to use conventional vias to make electrical contact to the lower electrode within the substrate.
      • For claim 16 (sloped sidewalls), Petitioner pointed to Kuboi's disclosure of using a "Bosch process" to create concavo-convex shapes on the hole sidewalls to improve sensitivity. Petitioner argued it would have been obvious to apply this disclosed technique to the primary embodiment to gain the stated benefits.

    • Expectation of Success (for §103 grounds): Petitioner asserted that a POSITA would have had a reasonable expectation of success in making these modifications. The proposed changes, such as using standard wiring layers, implementing vias for electrical connections, or applying a disclosed etching process (Bosch process), all relied on well-understood, predictable, and common techniques in CMOS image sensor fabrication.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-4, 7, 9-12, 16-17, 20-21, 24-26, 28-30, 32, and 35 of the ’700 patent as unpatentable.