PTAB

IPR2025-01009

Micron Technology Inc v. Palisade Technologies LLP

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Non-Volatile Storage Device and Method of Fabricating
  • Brief Description: The ’314 patent discloses non-volatile memory devices and fabrication methods intended to mitigate voltage breakdown issues in high-density arrays. The invention describes a memory cell structure with specific protective layers, including first oxide regions covering charge storage region sidewalls and a layered structure of second oxide and nitride regions covering word line sidewalls.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kang - Claims 1, 3-4, 6-7, 13, 17, and 19 are obvious over Kang.

  • Prior Art Relied Upon: Kang (Patent 7,598,564).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Kang, which aims to protect control gates from damage during fabrication, discloses all limitations of the challenged claims. Kang teaches word lines comprising a charge storage region (floating gate 5b) and a control gate (20b). Petitioner contended that Kang’s thermal oxide layer (31) covering the floating gate sidewalls constitutes the claimed "first oxide regions." Further, Kang’s "second barrier spacers" (26b) on the upper word line sidewalls, which include a medium-temperature oxide (MTO) layer (23b) and a silicon nitride layer (25b), were asserted to meet the limitations of the "second oxide regions" and "nitride regions," respectively.
    • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
    • Expectation of Success (for §103 grounds): Not applicable.
    • Key Aspects: Petitioner asserted that Kang’s spacers (35), which fill gaps between word lines, are electrical isolation regions made of materials other than silicon nitride, meeting the final limitation of independent claim 1.

Ground 2: Obviousness over Kang in view of Kang-1 - Claims 1-2, 5-6, 14, and 18 are obvious over Kang in view of Kang-1.

  • Prior Art Relied Upon: Kang (Patent 7,598,564) and Kang-1 (Application # 2007/0096202).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground relied on Kang’s disclosure as detailed in Ground 1 and supplemented it with Kang-1 for specific limitations, particularly for claim 2’s requirement of "a plurality of air gaps" for electrical isolation. Kang-1 explicitly teaches forming air gaps between adjacent gate structures to reduce parasitic capacitance, a well-known problem in memory devices. Petitioner argued that modifying Kang’s solid spacers (35) to be air gaps as taught by Kang-1 would have been an obvious design choice. For claim 5, Petitioner argued it would be obvious to substitute Kang’s conductive floating gate with a dielectric charge trapping region, as Kang-1 teaches these are two well-known, interchangeable options for non-volatile memory.
    • Motivation to Combine (for §103 grounds): A POSITA would combine these references to solve the known problem of parasitic capacitance. Kang-1 directly addresses this issue by teaching the use of low-dielectric materials, like air, for isolation. Because the references address complementary aspects of memory device performance (Kang on WL resistance, Kang-1 on capacitance) and share common inventors, a POSITA would look to both for solutions.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as combining the teachings involved the simple and predictable modification of replacing a solid spacer material with air gaps, a known technique to achieve the desired reduction in capacitance.

Ground 3: Obviousness over Purayath - Claims 1-2, 4-6, 13-14, and 18-19 are obvious over Purayath.

  • Prior Art Relied Upon: Purayath (Application # 2011/0309425).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Purayath alone discloses a memory device structure meeting all limitations. Purayath teaches forming layer stack rows with charge storage regions (466) and control gates (452), with word lines formed from the silicided upper portion (453) of the control gates. Petitioner mapped Purayath’s dielectric liner (486), described as an oxide, to both the "first oxide regions" (covering the charge storage region sidewalls) and the "second oxide regions" (covering the word line/control gate sidewalls). Purayath’s capping layer (488), which can be nitride, was mapped to the "nitride regions." Finally, Purayath explicitly teaches forming air gaps (487) between word lines for electrical isolation, meeting the limitations of claims 1 and 2.
    • Motivation to Combine (for §103 grounds): Not applicable (single reference ground).
    • Expectation of Success (for §103 grounds): Not applicable.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) against dependent claims 3, 7, and 17 over Purayath in view of Murata (Patent 7,759,722). This ground argued a POSITA would have been motivated to implement Purayath’s structure using the specific materials taught by Murata, such as tungsten for word lines and distinct silicon oxide and silicon nitride insulating films, as these were common, interchangeable, and well-understood materials for improving device performance.

4. Key Claim Construction Positions

  • Petitioner stated that no terms required explicit construction but noted the ’314 patent provides definitions for key terms. Specifically, the patent defines "covered" and "adjacent" as not requiring direct physical contact. Petitioner argued the prior art reads on the plain meaning of the claims, inclusive of these definitions.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-7, 13-14, and 17-19 of the ’314 patent as unpatentable.