PTAB

IPR2025-01015

Qualcomm Inc v. Collabo Innovations Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Microcontroller for Controlling Power Shutdown Process
  • Brief Description: The ’575 patent discloses a microcontroller designed to reduce power consumption by shutting down power to its CPU during standby mode. To address the problem of long restoration times caused by the loss of the CPU's internal state, the system saves the working context before power is cut off and restores it upon wake-up, enabling a quick resumption of operations.

3. Grounds for Unpatentability

Ground I: Claims 1, 3, 5, 8, 11, 12, 15, and 16 are obvious over Lee in view of Jahagirdar.

  • Prior Art Relied Upon: Lee (Patent 7,293,183) and Jahagirdar (Patent 7,664,970).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lee discloses the fundamental invention: a single-chip system-on-a-chip (SOC) with a microprocessor (CPU), memory (information holding unit), and power controllers that saves the CPU’s working context before entering a power-off standby mode and restores it upon exiting. Petitioner contended that while Lee teaches the core system architecture and process, it omits routine implementation details for clock control and the specific mechanism for executing the save/restore functions. Jahagirdar was asserted to supply these missing details by teaching a processor that uses a dedicated clock generator to manage clock signals during power state transitions and employs microcode (the claimed "microprogram") to efficiently execute the save and restore operations.
    • Motivation to Combine: Petitioner argued a POSITA implementing Lee's power-saving SOC would naturally consult analogous art like Jahagirdar to find well-understood solutions for the functions Lee described at a high level. Both references address power reduction in digital systems by cutting power and saving state. A POSITA would combine the teachings because Jahagirdar’s use of microcode offered a superior solution with greater flexibility and lower latency compared to less efficient hardware-based or program-based alternatives.
    • Expectation of Success: A POSITA would have a high expectation of success, as integrating a clock generator into an SOC and using microcode for state management were described as routine, well-established, and predictable procedures in digital system design.

Ground V: Claims 1, 5, 11, 12, and 15 are obvious over Shikata in view of Crump.

  • Prior Art Relied Upon: Shikata (Patent 7,219,248) and Crump (Patent 5,530,879).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Shikata discloses a single-chip processor containing a CPU core unit, internal RAM, and a voltage controlling unit that saves its working context before entering standby mode, thereby teaching the invention's essence. Similar to the argument against Lee, Petitioner contended Shikata omits specific details regarding how the save/restore process is triggered and executed. Crump allegedly provides these missing details by teaching the use of a system management interrupt (SMI) signal to alert the CPU to begin the context-saving process and the use of microcode to perform the save and restore operations.
    • Motivation to Combine: A POSITA tasked with implementing Shikata’s processor would be motivated to incorporate the established techniques from Crump. Both references are analogous art focused on power conservation. Using an interrupt signal like Crump's SMI to trigger the save routine was a standard industry practice. Furthermore, employing microcode was an advantageous method that aligned with Shikata’s design goal of minimizing hardware alterations while efficiently managing register values.
    • Expectation of Success: Success would be predictable. Petitioner argued that interrupt signals were a well-established communication method for processors, and microcode was a conventional and reliable technique for implementing save-and-restore functions, making the combination straightforward for a POSITA.

  • Additional Grounds: Petitioner asserted additional obviousness challenges by adding a third reference to the primary combinations to meet specific claim limitations. These grounds included adding Peterson (Patent 5,502,689) for claim 2, Kang (Patent 7,369,815) for claim 3, Higashida (Patent 7,167,991) for claim 11, and Chung (Patent 5,390,350) for claim 16.

4. Key Claim Construction Positions

  • "microcontroller": Petitioner argued this term must be construed as "a single integrated chip as opposed to a set of multiple chips (a ‘chipset’)." This position was based on the doctrine of judicial estoppel, asserting that the Patent Owner made clear and unmistakable disclaimers during prior IPR proceedings (the "AMD IPRs"). In those cases, the Patent Owner successfully argued that "microcontroller" required a single-chip implementation to distinguish the claims from multi-chip prior art, and the PTAB expressly relied on this construction in its decision not to institute.
  • "microprogram": Petitioner proposed construing this term as "a control program (or a microcode) that runs at the lowest level of the hardware... and is held entirely within the CPU as opposed to a program that is held in main memory until executed." This construction was also based on the Patent Owner's arguments in the AMD IPRs, where it distinguished the claimed "microprogram" from higher-level software "programs" to overcome prior art. Petitioner contended these statements constitute a binding disclaimer.
  • "power shutdown microprogram" / "power supply restoration microprogram": Based on the claim language and specification, Petitioner proposed constructions defining these terms as microprograms that necessarily perform the specific functions of evacuating/restoring information and outputting control signals as recited in the claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5, 8, 11, 12, 15, and 16 of the ’575 patent as unpatentable.