PTAB

IPR2025-01053

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device
  • Brief Description: The ’779 patent discloses a semiconductor device comprising at least two metal-insulator-semiconductor (MIS) transistors of an identical conductivity type on a single substrate. The asserted novelty is that the gate insulating film of a first transistor includes an interface layer that is thicker than the interface layer of a second transistor, thereby creating transistors with different threshold voltages on the same chip.

3. Grounds for Unpatentability

Ground I: Anticipation over Torii - Claims 1, 2, 7, 12, and 13 are anticipated by Torii under 35 U.S.C. §102.

  • Prior Art Relied Upon: Torii (Patent 6,881,657).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Torii discloses every limitation of the challenged claims. Torii teaches a semiconductor device with multiple MIS transistors on a single substrate, including a low-standby-power (LSTP) transistor and a low-operating-power (LOP) transistor, both of the same n-type conductivity. Petitioner mapped the LSTP transistor as the claimed "first MIS transistor" and the LOP transistor as the "second MIS transistor." Torii’s first transistor (LSTP) has a silicon oxynitride interface layer (film 24) that is "about 1.3 nm" thick, which is larger than the second transistor's (LOP) interface layer (film 22) of "about 0.9 to 0.95 nm." Both transistors use a high-k dielectric film (hafnia film 28) on their respective interface layers. For dependent claims, Torii was argued to disclose insulating spacers (inner spacers 36) that are thinner (5 nm) than other insulating spacers (middle nitride layers 38b, 25 nm), and that its high-k films contain hafnium and are of equal thickness (3.0 nm).

Ground II: Obviousness over Gilmer - Claims 1, 12, and 13 are obvious over Gilmer under 35 U.S.C. §103.

  • Prior Art Relied Upon: Gilmer (Patent 6,787,421).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Gilmer discloses a semiconductor device with transistors in a core region and an I/O region on a single substrate, utilizing dual gate dielectric thicknesses. Gilmer’s I/O transistor (first transistor) has a first interface layer (gate dielectric 16) with a thickness of 3-5 nm, which is larger than the core transistor's (second transistor) second interface layer (gate dielectric 20) with a thickness of 0.4-1.2 nm. Gilmer further teaches that both interface layers are silicon dioxide or silicon oxynitride, and a single high-k dielectric layer (metal oxide 26), preferably hafnium oxide, is deposited over both.
    • Motivation to Combine (for §103 grounds): This is a single-reference ground. The motivation relates to the only element Petitioner argued Gilmer does not explicitly state: that the two transistors are of an identical conductivity type. Petitioner argued a person of ordinary skill in the art (POSITA) would have been motivated to make the transistors the same conductivity type because it was one of only two simple design choices (same vs. different conductivity type) and a common practice for comparing I/O and core transistor characteristics.
    • Expectation of Success: A POSITA would have a high expectation of success, as fabricating multiple transistors of the same conductivity type on a single substrate was a well-known, routine, and predictable aspect of semiconductor design long before the ’779 patent.

Ground III: Obviousness over Gilmer and Chen - Claims 1, 12, and 13 are obvious over Gilmer in view of Chen under §103.

  • Prior Art Relied Upon: Gilmer (Patent 6,787,421) and Chen (Patent 7,382,023).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted this ground in the alternative, arguing that if Gilmer is found not to teach or suggest transistors of the same conductivity type, Chen explicitly supplies this element. Gilmer provides the primary device structure with dual-thickness interface layers and a high-k dielectric, as detailed in Ground II. Chen was introduced to teach forming core and I/O transistors on the same substrate that have "the same conductivity type," such as two pMOS transistors or two nMOS transistors with different threshold voltages.
    • Motivation to Combine: A POSITA would combine Gilmer's structure with Chen's teachings to implement a known transistor configuration (same-type core and I/O transistors from Chen) into an advanced dual-dielectric architecture (from Gilmer). Both references are in the same field and address the common problem of integrating transistors with different performance characteristics onto a single chip. Combining them represented a predictable path to optimizing device performance.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because the combination involves the application of a known design principle from Chen (using same-type transistors for different functions) to the analogous device structure in Gilmer. This modification did not present any apparent technical hurdles.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 2, 7, 12, and 13 of Patent 8,796,779 as unpatentable.