PTAB

IPR2025-01054

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Non-Planar Semiconductor Devices with Epitaxial Structures
  • Brief Description: The ’193 patent discloses FinFET semiconductor devices featuring raised source/drain structures formed through epitaxial growth. The purported novelty resides in forming an additional "cap" layer on the epitaxial source/drain structures, wherein the caps on adjacent structures are configured to merge together.

3. Grounds for Unpatentability

Ground 1: Obviousness over Glass - Claims 1-5, 7-9, and 11 are obvious over Glass.

  • Prior Art Relied Upon: Glass (Patent 10,535,735).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Glass, which describes a FinFET architecture designed to minimize parasitic resistance, discloses all limitations of the challenged claims. Specifically, Glass teaches a boron-doped germanium-tin alloy layer disposed between its primary epitaxially grown source/drain layer and the contact stack. Petitioner contended this alloy layer constitutes the claimed "cap," and the underlying source/drain layer is the claimed "epitaxial structure."
    • Motivation to Combine (for §103 grounds): This ground is based on a single reference. Petitioner asserted that the claimed feature of merging adjacent caps would have been obvious from Glass's disclosure. A POSITA would have understood that depositing the cap layers concurrently from the same material, as taught by Glass, would cause them to merge, particularly when applying fin pitch and layer thickness values that were well-known in the art. The motivation for ensuring such a merge was to reduce source/drain contact resistance and relax photolithography requirements for patterning contacts, both known benefits of merged structures.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in achieving merged caps by simply selecting known process parameters.

Ground 2: Obviousness over Glass and Tsai - Claim 6 is obvious over Glass in view of Tsai.

  • Prior Art Relied Upon: Glass (Patent 10,535,735), Tsai (Patent 7,538,387).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that while Glass provides the basic FinFET structure with merged caps, it does not explicitly disclose the three-part epitaxial structure recited in claim 6 ("a low doped epitaxial layer, a high doped epitaxial layer and a liner"). Tsai was argued to supply this missing element. Tsai teaches using a three-layer "sandwich structure" for its SiGe stressors in source/drain regions, comprising layers with varying dopant and germanium concentrations that directly correspond to the claimed liner, low-doped, and high-doped layers.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Tsai’s layered stressor with Glass’s FinFET to improve device performance, a key goal of both references. Tsai specifically addresses drawbacks of conventional stressors (like those in Glass) where high dopant concentrations can lead to lateral diffusion and degrade short-channel characteristics. Tsai’s use of a low-impurity layer as a diffusion barrier would have been seen as a known solution to a known problem, applicable to the Glass device.
    • Expectation of Success (for §103 grounds): Success was predictable, as Tsai’s method utilizes conventional epitaxial growth techniques that were routinely applied in FinFET fabrication.

Ground 3: Obviousness over Kelly and Murthy - Claims 1-10 are obvious over Kelly in view of Murthy.

  • Prior Art Relied Upon: Kelly (Patent 8,703,556), Murthy (Patent 8,598,003).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Kelly discloses a multi-fin FinFET with epitaxial source/drain structures that can be fabricated to either remain separate or merge, depending on process parameters. However, Kelly does not teach a distinct cap layer. Murthy was argued to disclose a two-part source/drain structure comprising a lower epitaxial region and an outer "cap layer" deposited over it. The proposed combination applies Murthy's two-part structure (epitaxial layer + cap) to Kelly's multi-fin device, resulting in adjacent caps that merge while the underlying epitaxial structures remain spaced apart.
    • Motivation to Combine (for §103 grounds): A POSITA would be motivated to add Murthy's cap layer to Kelly's device to enhance performance. Kelly expressly stated its device "may include additional features" formed by subsequent processing. Murthy's cap layer was taught to provide several known benefits, including reduced parasitic resistance and the introduction of beneficial tensile stress, which were directly aligned with Kelly's stated goal of improving FinFET device performance. The combination represented the use of a known technique (adding a cap) to improve a similar device.
    • Expectation of Success (for §103 grounds): Both references describe similar FinFET devices and employ common, well-understood deposition methods. A POSITA would have reasonably expected that Murthy’s cap could be successfully integrated into Kelly’s process flow to yield predictable improvements.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge that claim 11 is obvious over the combination of Kelly, Murthy, and Liaw (Patent 8,399,931), where Liaw provides the motivation and means for adding the claimed final dielectric and contact structures. A challenge against claims 1, 7, and 10 was also asserted based on Su (Application # 2011/0210404), which discloses a multi-step deposition-etch process that forms a merged outer cap layer over non-merged inner epitaxial structures to eliminate voids.

4. Relief Requested

  • Petitioner requests the institution of an inter partes review and cancellation of claims 1-11 of the ’193 patent as unpatentable.