PTAB

IPR2025-01090

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with Stress-Relief Structures
  • Brief Description: The ’425 patent relates to semiconductor devices, specifically metal-insulator-semiconductor field-effect transistors (MISFETs), that incorporate stress-inducing and stress-relief structures. The technology aims to improve device performance by mitigating the negative impact of a tensile stress insulating film on a PMOS transistor’s channel region through the use of a dedicated stress-relief film.

3. Grounds for Unpatentability

Ground 1: Obviousness over Wu922 and Alvarez - Claims 1, 3, 4, 7, 8, and 11 are obvious over Wu922 in view of Alvarez.

  • Prior Art Relied Upon: Wu922 (Application # 2009/0246922) and Alvarez (Application # 2007/0249069).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Wu922 discloses a strained CMOS transistor with all the basic components of claim 1, including raised silicon-germanium (SiGe) source/drain regions in its PMOS devices to create compressive stress and a contact etch-stop layer (CESL) that covers the device. Alvarez addressed the known problem where a tensile CESL (used to improve NMOS performance) degrades PMOS performance. Alvarez taught solving this by forming a "stress-controlling layer" (e.g., silicon oxide) underneath the tensile CESL, specifically in the space between the SiGe regions and the gate sidewall spacer. This stress-controlling layer functions as the claimed "stress-relief film."
    • Motivation to Combine: A POSITA would combine these references to improve the overall performance of Wu922’s CMOS device. A POSITA would have been motivated to make Wu922’s CESL tensile to boost NMOS performance (a common industry practice) and would have simultaneously looked to prior art like Alvarez for a solution to the known adverse effects on the PMOS transistor. Alvarez provided an express solution: adding a stress-controlling layer to buffer the unwanted tensile stress, which also streamlined manufacturing by selectively blocking silicide formation.
    • Expectation of Success: The combination required only conventional deposition and patterning techniques to add Alvarez's stress-relief layer into the gap created by Wu922's existing process flow. A POSITA would have reasonably expected this combination to yield the predictable result of buffering CESL strain on the PMOS device while improving the NMOS device.

Ground 2: Obviousness over Cheng817 and Wang906 - Claims 1, 3, 4, 7, 8, and 11 are obvious over Cheng817, alone or in view of Wang906.

  • Prior Art Relied Upon: Cheng817 (Application # 2005/0112817) and Wang906 (Application # 2007/0034906).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Cheng817 discloses all elements of the challenged claims when its disclosures are properly interpreted. Petitioner argued that a key figure in Cheng817 contains a rendering error, and that a POSITA, potentially aided by analogous art like Wang906, would understand the correct structure. In this corrected view, the raised SiGe source/drain regions grow up and around the sidewalls, not through them. This process creates a space that is filled by "dummy spacers" made of silicon dioxide, which Petitioner argued meet the limitations of the claimed "first stress-relief film." Cheng817 further disclosed a tensile etch stop layer over the device, meeting the "stress insulating film" limitation.
    • Motivation to Combine: The primary argument is that a POSITA would find the claimed invention obvious from Cheng817's disclosures alone once its figures are reconciled with its text. Wang906, which describes a similar process, was used to demonstrate how a POSITA would have understood the proper formation of raised SiGe regions and sidewall structures, thereby confirming the interpretation of Cheng817's disclosure as teaching the claimed invention.
    • Expectation of Success: A POSITA would have understood that the structure described in Cheng817's text, which uses standard semiconductor features, would function as claimed to manage transistor stress.

Ground 3: Obviousness over Saito825, Fukutome, and James - Claims 1, 3, 4, 7, and 8 are obvious over Saito825 in view of Fukutome and James.

  • Prior Art Relied Upon: Saito825 (Application # 2008/0029825), Fukutome (Application # 2005/0285203), and James (a 2005 IEEE conference paper).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued this combination provides all elements of the claims. Saito825 discloses a base SRAM transistor structure, including the use of silicon oxide to fill recesses in isolation regions adjacent to the transistor. Fukutome teaches an improvement for PMOS devices by replacing standard source/drains with raised, faceted epitaxial SiGe to create beneficial compressive stress. James teaches that applying a tensile stressed silicon nitride layer (CESL) is a well-known, inexpensive method to improve NMOS device performance. The proposed combination substitutes Fukutome's raised SiGe into Saito825's PMOS transistor and makes Saito825's nitride layer tensile per James.
    • Motivation to Combine: A POSITA would have been motivated to combine these known techniques to improve the performance of Saito825’s standard SRAM device. It was a simple case of substituting a known, superior element (Fukutome's raised SiGe) for an old one to improve PMOS performance, and applying a known technique (James's tensile CESL) to improve NMOS performance. The silicon oxide disclosed by Saito825 for filling recesses would then naturally and inherently be located between the raised SiGe facets and sidewalls, serving as a buffer—the claimed "stress-relief film"—to mitigate the unwanted tensile stress on the improved PMOS device.
    • Expectation of Success: The combination involved substituting known elements for their known purposes (improving performance) and would predictably result in an improved SRAM device. James confirmed the commercial success of using both raised SiGe and a tensile CESL together.

4. Relief Requested

  • Petitioner requested that an inter partes review be instituted and that claims 1, 3, 4, 7, 8, and 11 of the ’425 patent be cancelled as unpatentable.