PTAB

IPR2025-01091

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device with n- and p-type MIS Transistors
  • Brief Description: The ’686 patent relates to a semiconductor device with complementary metal-insulator-semiconductor field-effect transistors (MISFETs), specifically n-type and p-type transistors that have gate electrodes made of different metal materials. The technology also involves using strain engineering, such as forming silicon-germanium (SiGe) in source/drain regions and applying stressed films, to enhance transistor performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Aoyama and Hsu823 - Claims 25-28, 31, and 35 are obvious over Aoyama in view of Hsu823.

  • Prior Art Relied Upon: Aoyama (Application # 2007/0215950) and Hsu823 (Application # 2007/0235823).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Aoyama teaches a semiconductor device with both n-type (NMOS) and p-type (PMOS) transistors, each having distinct metal gate electrodes over a high-k gate dielectric film. Aoyama’s structure allegedly discloses most limitations of independent claim 25, including different metal films for the NMOS (TaCN) and PMOS (TiN) gates (claim 27), the use of the same high-k gate insulating film for both transistors (claim 31, claim 35), and a planarization process that results in different metal film thicknesses (claim 26). Petitioner further argued that Hsu823 teaches two key performance-enhancing techniques not explicitly shown in Aoyama: (1) forming epitaxial SiGe stressors in recessed PMOS source/drain regions to induce compressive channel stress, and (2) using a tensile contact etch-stop layer (CESL) to apply tensile stress to the NMOS channel. The combination of Aoyama's silicon nitride film with Hsu823's teaching of tensile stress satisfies the stress limitation of claim 25. For claim 28, Petitioner argued that Aoyama’s figures show the silicon nitride film is thinner than the gate electrode, which is an inherently obvious design choice due to the physical constraints of planarization and the known, disparate thicknesses of gate vs. interlayer dielectrics.
    • Motivation to Combine: A POSITA would combine the teachings of Hsu823 with Aoyama's device for the predictable and well-known benefits of improved transistor performance. Specifically, incorporating Hsu823's SiGe stressors into Aoyama's PMOS transistor was a known method to increase hole mobility and drive current. Similarly, a POSITA would have been motivated to ensure Aoyama’s silicon nitride film possessed tensile properties, as taught by Hsu823, to improve NMOS electron mobility.
    • Expectation of Success: Petitioner asserted a high expectation of success. By the priority date of the ’686 patent, using SiGe stressors and tensile CESL films were standard, widely-adopted industry practices for improving transistor performance, with multiple generations of commercial devices already incorporating these techniques.

Ground 2: Obviousness over Akasaka and Hsu823 - Claims 25-28, 31, and 35 are obvious over Akasaka in view of Hsu823.

  • Prior Art Relied Upon: Akasaka (Application # 2007/0066077) and Hsu823 (Application # 2007/0235823).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Akasaka discloses a MISFET device with n-type and p-type transistors fabricated using a replacement metal gate (RMG) process. This process results in distinct metal gate electrodes for each transistor type, sidewall spacers, and a silicon nitride etch-stop layer, thereby meeting the fundamental elements of the challenged claims. Akasaka discloses different metal films for the PMISFET (e.g., TiN with a work function of 4.8-5.3 eV) and NMISFET (e.g., a metal with a work function of 3.9-4.2 eV), which also have different thicknesses (claims 26-27). Akasaka further discloses depositing its gate dielectric (HfSixOy) over the entire substrate, satisfying the limitations for a common insulating material (claim 31) and a high-k film (claim 35). As in Ground 1, Hsu823 provides the missing teachings for incorporating compressive SiGe stressors in the PMOS device and applying tensile stress via the CESL in the NMOS device.
    • Motivation to Combine: The motivation is parallel to Ground 1 but applied to Akasaka's base structure. A POSITA would have been motivated to modify Akasaka's device by forming epitaxial SiGe stressors in the PMISFET source/drain regions, as taught by Hsu823, to achieve the known benefit of increased hole mobility and operating speed. The silicon nitride etch-stop film in Akasaka would be formed to be tensile, per Hsu823, to improve NMOS performance.
    • Expectation of Success: Petitioner again argued for a high expectation of success because the device structures in Akasaka and Hsu823 were materially similar. The integration of SiGe stressors and the implementation of a tensile CESL were well-understood, predictable processes to boost transistor performance and would have been readily implemented by a POSITA in Akasaka’s device.

4. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 25-28, 31, and 35 of the ’686 patent as unpatentable.