PTAB

IPR2025-01092

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method for Manufacturing the Same
  • Brief Description: The ’180 patent relates to techniques for improving the performance and reliability of a metal insulator semiconductor field-effect transistor (MISFET). The claimed invention involves a high dielectric constant (high-k) gate insulating film that extends from under the gate electrode to beneath an insulating sidewall, where the film’s end is located a predetermined distance inward from the sidewall’s outer edge.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 5-6, 13-14, 16-19, and 21-22 are obvious over Kamata.

  • Prior Art Relied Upon: Kamata (Application # 2002/0063299).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kamata’s various embodiments disclose every limitation of the challenged claims. Specifically, Kamata’s devices include a gate electrode, a high-k gate insulating film, and a multi-layer insulating sidewall structure on a substrate. The gate insulating film is shown to be continuously formed, extending from under the gate electrode to under at least a portion of the insulating sidewall. Critically, Kamata’s figures and manufacturing process show the end of this high-k film is located inwardly from the outer end of the insulating sidewall, satisfying the key "predetermined distance" limitation of claim 1.
    • Prior Art Mapping (Dependent Claims): Petitioner asserted that Kamata further teaches the limitations of the dependent claims. For claims 2-3, Kamata discloses an optional silicon oxide buffer layer. For claims 5, 21, and 22, Kamata’s ninth embodiment discloses a tapered gate insulating film whose thickness decreases under the sidewall. For claims 6 and 18-19, Kamata expressly lists Hf-based oxides (with a dielectric constant >10) as a material for the high-k film, and silicon oxide and silicon nitride for the sidewall films (with dielectric constants <10). For claims 16-17, Kamata’s figures show the high-k film is wider than the gate electrode.

Ground 2: Claims 1-3, 5-6, 13-14, 16-18, and 21-22 are obvious over Guha.

  • Prior Art Relied Upon: Guha (Application # 2006/0091432).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Guha’s Figure 12 device discloses a semiconductor structure meeting all limitations of independent claim 1. Guha teaches a gate electrode formed over a high-k dielectric layer, which in turn is on a gate-isolating buffer layer. The device includes gate spacers (an "insulating sidewall") on the sides of the gate electrode. The high-k dielectric layer extends continuously from under the gate to under the inner gate spacer. The end of this high-k layer is rounded or tapered and located inward from the outer edge of the full sidewall structure, meeting the "predetermined distance" limitation.
    • Prior Art Mapping (Dependent Claims): Petitioner argued Guha also discloses the dependent claim limitations. Claims 2-3 are met by Guha's gate-isolating layer, which acts as a buffer and is preferably silicon oxide. Claims 5, 21, and 22 are met by the rounded/tapered edge of the dielectric layer, which reduces in thickness. Claim 6 is met by Guha’s disclosure of hafnium oxide for the high-k layer. Claim 14 is met by the sidewall structure composed of an inner oxide spacer and an outer nitride spacer.

Ground 3: Claim 11 is obvious over Kamata in view of Sim.

  • Prior Art Relied Upon: Kamata (Application # 2002/0063299) and Sim ("Effects of ALD HfO2 thickness on charge trapping and mobility," a 2005 journal article).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Kamata discloses all limitations of claim 1, which claim 11 depends from, but does not expressly state that the high-k gate dielectric under the sidewall has a thickness of 2 nm or less. Sim, which systematically evaluated the effects of high-k film thickness, explicitly discloses that a high-k gate insulating film (specifically HfO2) with a thickness of 2 nm (20Å) or less improves device performance.
    • Motivation to Combine: A POSITA would combine Sim’s teaching of an optimal film thickness with Kamata’s device structure to achieve known benefits. Sim expressly found that reducing HfO2 thickness to below 2 nm enhances carrier mobility and reduces charge trapping, addressing key challenges in semiconductor scalability that were well-known at the time and relevant to the goals of Kamata.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because the combination involves applying a known technique (using a thinner, performance-enhancing dielectric layer) to a conventional device structure. Sim confirms the predictability of the outcome using a standard atomic layer deposition (ALD) process for fabricating the thin film.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including claims 18-19 over Kamata in view of Wilk (a 2001 journal article), claim 11 over Guha in view of Sim, and claims 1, 5, 13-14, and 16-19 over Matsumoto (Application # 2003/0025135). These grounds relied on similar arguments, using Wilk to provide dielectric constant values for materials in Kamata and Matsumoto to show another complete device structure.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-6, 11, 13-14, 16-19, and 21-22 of the ’180 patent as unpatentable.