PTAB

IPR2025-01093

United Microelectronics Corp v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method of Manufacturing the Same
  • Brief Description: The ’076 patent relates to techniques for improving the driving power and reliability of a Metal Insulator Semiconductor Field-Effect Transistor (MISFET). The purported invention achieves this by extending a high-k gate insulating film from under the gate electrode to under a sidewall, where the end of the film is retracted from the outer edge of the sidewall.

3. Grounds for Unpatentability

Ground I: Claims 1-3, 7-8, and 10-13 are obvious over Kamata

  • Prior Art Relied Upon: Kamata (Application # 2002/0063299).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kamata’s disclosed embodiments teach all limitations of the challenged claims. Specifically, Kamata’s figures depict a semiconductor device with a high-k gate insulating film (disclosing hafnium (Hf) as a possible material) that extends from under a gate electrode to underneath a multi-layer insulating sidewall structure. Petitioner asserted that Kamata’s figures clearly show the end of this gate insulating film is disposed inward, or "retracted," from the outer end of the insulating sidewall, thereby meeting the core limitations of independent claim 1. Kamata was also argued to disclose a buffer insulating film (claim 2), a double-layer sidewall with an oxide and a nitride film (claim 8), and a tapered end surface of the insulating film (claims 11-12).
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the argument was that Kamata itself renders the claims obvious. Petitioner contended a person of ordinary skill in the art (POSITA) would have been motivated to select HfO2 from the list of high-k materials disclosed by Kamata due to its well-known benefits, such as superior thermal stability.

Ground II: Claim 6 is obvious over Kamata in view of Sim

  • Prior Art Relied Upon: Kamata (Application # 2002/0063299) and Sim (a 2005 journal article titled “Effects of ALD HfO2 thickness on charge trapping and mobility”).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that while Kamata taught the structure of claim 1, it did not explicitly disclose that a part of the gate insulating film under the sidewall has a thickness of 2 nm or less, as required by claim 6. The Sim reference, which systematically evaluated the effects of high-k film thickness, was argued to supply this missing element by teaching that scaling the physical thickness of an HfO2 dielectric to below 20Å (2 nm) reduces charge trapping and enhances carrier mobility.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Sim’s teaching with Kamata’s device to improve performance and scalability. Petitioner argued this was a predictable solution to a known problem (improving device characteristics during miniaturization) and aligned with the goals of advancing CMOS technology emphasized in both references.
    • Expectation of Success (for §103 grounds): Success would have been predictable because Sim used a well-known, conventional process—atomic layer deposition (ALD)—for fabricating the thin high-k films.

Ground III: Claims 1-3, 7-8, and 10-13 are obvious over Guha

  • Prior Art Relied Upon: Guha (Application # 2006/0091432).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Guha, as a single reference, rendered the challenged claims obvious. Guha’s device was shown to include a gate insulating film comprising a high-k material (e.g., hafnium oxide) formed on an active region. This film extended from beneath the gate electrode to under a gate spacer, which Petitioner equated to the claimed "insulating sidewall." Petitioner asserted that Guha’s figures show the end of this dielectric layer is rounded and located inward from the outer edge of an additional isolating spacer, satisfying the "retracted" limitation of claim 1. Guha was also argued to teach a buffer layer (claim 2), a double-layer sidewall structure (claim 8), and a tapered end surface (claims 11-12).

Ground V: Claims 1-3, 7-8, 10, and 13 are obvious over Matsumoto in view of Yu

  • Prior Art Relied Upon: Matsumoto (Application # 2003/0025135) and Yu (Patent 6,504,214).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Matsumoto disclosed the core structure of claim 1—a MOSFET with a gate insulating film extending under an insulating sidewall—but did not explicitly require an Hf-based oxide or a buffer layer. Yu was argued to provide these missing elements by teaching the use of hafnium oxide as a high-k gate dielectric and disclosing a thin silicon oxide buffer interface between the substrate and the high-k film.
    • Motivation to Combine (for §103 grounds): A POSITA would have been motivated to replace Matsumoto’s generic high-k dielectric with Yu’s specific teaching of hafnium oxide to achieve its known benefits. Furthermore, Petitioner argued a POSITA would integrate Yu’s buffer layer into Matsumoto’s device to achieve Yu's explicitly stated goals of reducing atomic diffusion and improving channel mobility, thereby enhancing the overall performance of the combined device.
    • Expectation of Success (for §103 grounds): The combination would have yielded predictable results because Yu taught conventional techniques for creating the buffer layer, presenting a straightforward application of a known element to improve a similar device.
  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations of Guha-Sim, Matsumoto-Yu-Sim, Matsumoto-Koyama, and Matsumoto-Ono but relied on similar arguments for improving device performance and incorporating known features.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 6-8, and 10-13 of the ’076 patent as unpatentable.