PTAB

IPR2025-01210

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Fabrication Method Using Dummy Vias to Reduce Stress
  • Brief Description: The ’751 patent discloses a method for fabricating multilevel semiconductor interconnect structures. The method involves forming a dummy via, which is incapable of carrying current, adjacent to a functional via to reduce stress migration and suppress void formation by dividing and redirecting vacancies away from the functional via.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 5-8, 10-13, 18, and 20 are Anticipated by or Obvious over Watanabe

  • Prior Art Relied Upon: Watanabe (Application # 2003/0116852)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Watanabe, which addresses the same interconnect reliability problems as the ’751 patent, discloses every limitation of the challenged claims. Watanabe teaches using non-functional dummy structures in a dual-damascene process to mitigate stress-induced void migration and electromigration. Specifically, Watanabe’s "dummy plug 34" was asserted to be the claimed "dummy via," formed alongside a functional "conductive plug 32." The petition contended that Watanabe’s dummy plug is incapable of carrying current because one end connects to an active wiring layer while the other terminates in a "non-forming region" of an insulating film, directly corresponding to the core limitation of independent claim 1. Dependent claim features, such as multilayer insulating films (claim 5), square-shaped vias (claim 10), and specific spacing (claim 13), were also argued to be explicitly disclosed in various embodiments and figures of Watanabe.

Ground 2: Claims 1, 5-6, 9, 11-14, and 18-19 are Anticipated by Hasunuma

  • Prior Art Relied Upon: Hasunuma (Application # 2004/0113238)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Hasunuma anticipates the claims by teaching a method to form interconnect structures with dummy vias for reinforcing the structure against stress. Hasunuma’s "reinforcing plug 28" was mapped to the claimed "dummy via." These reinforcing plugs are formed simultaneously with a functional "conductive via plug 27" and a second interconnect ("conductive layer 26") using a dual-damascene process. Hasunuma was argued to meet the "incapable of having current flow" limitation by explicitly stating that its reinforcing plugs are "not electrically connected to the essential wiring layer." Further, Petitioner mapped various dependent claim limitations, including the use of circular vias (claim 9), the relative depth of dummy versus functional vias (claim 14), and the formation of the dummy via from the same conductive film as the second interconnect (claim 18).

Ground 3: Claims 3-4 and 15-16 are Obvious over Watanabe in view of Kamoshima

  • Prior Art Relied Upon: Watanabe (Application # 2003/0116852), Kamoshima (Application # 2004/0173905)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that while Watanabe discloses the fundamental structure of using functional and dummy vias, Kamoshima teaches the specific branched interconnect trench shape recited in claims 3, 4, 15, and 16. Kamoshima discloses an interconnect layer with a wide portion branching into a narrower portion. It further teaches arranging the functional via along the narrow portion while placing a dummy via near the "connection portion" (branch point) between the wide and narrow sections.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Kamoshima’s branched interconnect design with Watanabe’s method to more effectively suppress microvoids. Kamoshima presents this specific arrangement as a known design choice to improve reliability by controlling vacancy migration, which is the same problem addressed by Watanabe. The combination would thus represent an enhancement of Watanabe’s solution using a known technique for a predictable result.
    • Expectation of Success: A POSITA would have had a high expectation of success. The proposed modification only involved altering the shape of the interconnect trench during the etching step, a straightforward and well-understood adjustment to the manufacturing processes already disclosed in Watanabe and taught by Kamoshima.
  • Additional Grounds: Petitioner asserted numerous other challenges, including obviousness of various claims over Aoyagi (Application # 2001/0019180) and additional combinations of the primary references with Fukazawa (JP2002299437), Iizuka (Patent 5,250,465), and Kurashima (Patent 7,042,099).

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-20 of the ’751 patent as unpatentable.