PTAB

IPR2025-01211

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method for Manufacturing the Same
  • Brief Description: The ’623 patent discloses a semiconductor device with multilevel interconnects that incorporates "dummy vias." These non-functional, conductive structures are formed alongside active vias in a dual damascene process to reduce stress-induced void formation and improve the mechanical strength of the interconnect structure.

3. Grounds for Unpatentability

Ground 1A: Anticipation of Claims 10, 19-20, 24, and 27 by Watanabe

  • Prior Art Relied Upon: Watanabe (Application # 2003/0116852).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Watanabe discloses every element of the challenged claims. Watanabe teaches a multilevel dual-damascene interconnect structure designed to address stress migration and electromigration issues. It discloses a first interconnect (“wiring 36”), a second interconnect (“wiring 39”), a functional via connecting them (“conductive plug 32”), and a dummy via (“dummy plug 34”) also connected to the second interconnect. The dummy plug is shown extending into a "non-forming region" of an insulating film, rendering it incapable of current flow. For claim 27, Petitioner asserted Watanabe’s figures show the spacing between the active and dummy vias is substantially equal to the minimum interconnect width. Dependent claims reciting square vias (claims 10, 19, 20, 24) are allegedly met by Watanabe’s plan-view figures showing square-shaped plugs.

Ground 8: Anticipation of Claims 23, 27, 41, and 43-44 by Hasunuma

  • Prior Art Relied Upon: Hasunuma (Application # 2004/0113238).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Hasunuma anticipates the challenged claims by teaching a similar solution for mitigating stress in interconnect structures. Hasunuma discloses a first interconnect (“conductive layer 14”), a second interconnect (“conductive layer 26”), a functional via (“conductive plug 27”), and non-functional dummy vias (“reinforcing plugs 28”), all formed concurrently in a dual damascene process. The dummy vias are explicitly described as non-functional and terminate in an insulating film. For claim 23, Hasunuma is said to teach circular vias, referring to their "diameter" and providing figures showing circular plugs. For claim 27, Petitioner argued that the "Plug interval" disclosed in Hasunuma's tables, when combined with the stated via diameter, results in a via-to-dummy-via distance equal to the minimum interconnect width. For claim 43, Hasunuma’s figures allegedly show the bottom of the dummy via is located deeper than the bottom of the active via.

Ground 7: Obviousness of Claim 48 over Watanabe, Kamoshima, and Fukazawa

  • Prior Art Relied Upon: Watanabe (Application # 2003/0116852), Kamoshima (Application # 2004/0173905), and Fukazawa (JP2002299437).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued claim 48, which depends from claim 45, is obvious over the combination. Claim 45 requires a second interconnect comprised of a first (wider) portion and a second (narrower) portion, with the active via connected to the narrower portion. Claim 48 adds limitations that the dummy via is rectangular and its longer side is provided along the same direction as a longer side of the wider interconnect portion. Petitioner asserted Watanabe provides the basic dual-damascene structure with active and dummy vias. Kamoshima teaches a branched interconnect with wide and narrow portions to suppress microvoid concentration near the active via. Fukazawa teaches using rectangular dummy vias to enhance mechanical strength, specifically orienting the via’s longer side parallel to the interconnect’s longer side.
    • Motivation to Combine: A POSITA would combine Watanabe and Kamoshima to improve void suppression by adopting Kamoshima's known branched interconnect design. To further enhance mechanical strength and reliability—a known concern—a POSITA would have been motivated to implement the rectangular dummy vias taught by Fukazawa. Placing the rectangular dummy via on the wider portion of the interconnect, as taught by Fukazawa and Kamoshima (for analogous structures), would predictably improve mechanical support and vacancy interception.
    • Expectation of Success: A POSITA would have had a high expectation of success, as combining these elements involved known design choices to solve predictable problems. Modifying interconnect trench shapes and via patterns were standard, achievable modifications in semiconductor manufacturing.

  • Additional Grounds: Petitioner asserted numerous additional obviousness grounds. These included challenges based on Watanabe in view of Iizuka, Kurashima, Nasu, and Fujii, as well as challenges based on Hasunuma in view of Watanabe, Iizuka, Nasu, Kurashima, and Kamoshima. These grounds primarily relied on combining the base references (Watanabe or Hasunuma) with secondary art teaching well-known, interchangeable design alternatives for via shape (circular, square, rectangular), relative sizing, and spacing to achieve predictable improvements in manufacturing or reliability.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 5-6, 10, 19-20, 23-24, 27, 29-31, 33-38, 41, 43-44, and 48 of the ’623 patent as unpatentable.