PTAB

IPR2025-01212

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor device with multilevel interconnection structures
  • Brief Description: The ’623 patent discloses a semiconductor device that uses dummy vias in conjunction with functional interconnects and vias. These dummy structures are intended to reduce stress-induced void formation in multilevel copper interconnects, thereby improving device reliability.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-3, 7, 11-16, 21-22, 25-26, 28, 32, 39-40, and 42 under §102 by Watanabe

  • Prior Art Relied Upon: Watanabe (Application # 2003/0116852).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Watanabe discloses a semiconductor device with multilevel, dual-damascene interconnects that addresses the same reliability problems as the ’623 patent. Independent claim 1’s limitations were allegedly met by Watanabe’s embodiments, which show a first interconnect (“wiring 36”), a first insulating film, and a second interconnect (“wiring 39”) formed above it. Watanabe’s structure includes a functional via (“conductive plug 32”) connecting the interconnects and a non-functional dummy via (“dummy plug 34”) connected to the second interconnect. Petitioner asserted that Watanabe’s dummy via is made of a conductive film but is incapable of current flow because its other end terminates in a non-forming region of an insulating film, not completing a circuit. The interconnects, via, and dummy via were all shown to be formed using a dual damascene process. Petitioner contended that various embodiments in Watanabe disclose all limitations of the challenged dependent claims, including structures with dummy interconnects (claim 2) and specific material compositions (claims 11-13).

Ground 2: Obviousness of Claims 4 and 8 over Watanabe in view of Kurashima

  • Prior Art Relied Upon: Watanabe (Application # 2003/0116852) and Kurashima (Patent 7,042,099).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Watanabe’s fifth embodiment discloses a first dummy interconnect (“dummy wiring 61”) that has a slightly larger width than the first interconnect (“wiring 39”). For claim 4, which requires these widths to be substantially equal, Petitioner asserted that Kurashima explicitly teaches forming functional and dummy wires with substantially the same width to enhance the durability of insulating films against CMP-related stress. For claim 8, which requires the longer sides of the first interconnect and first dummy interconnect to form a right angle, Petitioner pointed to Kurashima’s teaching of using dummy wires with various shapes and orientations, including orthogonal arrangements, to reduce CMP stress and film peeling.
    • Motivation to Combine: A POSITA would combine Watanabe's dummy structures with Kurashima's teachings on interconnect sizing and orientation to improve mechanical strength and reduce parasitic capacitance and crosstalk. Kurashima showed that matching the widths of dummy and functional interconnects was a known design choice for ensuring secure connections and structural integrity.
    • Expectation of Success: A POSITA would have had a high expectation of success, as modifying interconnect widths and orientations was a routine design optimization involving standard patterning techniques.

Ground 3: Anticipation of Claims 1, 11-15, 17-18, 21-22, 25-26, 28, 32, and 39-40 under §102 by Hasunuma

  • Prior Art Relied Upon: Hasunuma (Application # 2004/0113238).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Hasunuma anticipates the challenged claims by disclosing a multilevel interconnect structure designed to solve stress-related reliability problems. Hasunuma’s device allegedly includes all elements of claim 1: a first interconnect (“conductive layer 14”), an insulating film stack, a second interconnect (“conductive layer 26”), a functional via (“conductive plug 27”), and a dummy via (“reinforcing plug 28”). Petitioner contended Hasunuma’s reinforcing plug is a conductive, non-functional structure incapable of current flow, as it terminates in an insulating layer and is explicitly described as a "dummy plug (sacrifice plug)." Hasunuma also explicitly teaches forming these structures using a dual damascene process. Petitioner further argued that Hasunuma discloses the features of the dependent claims, including the use of circular vias with specified diameters (claims 17-18) and specific via spacing (claims 25-26).

  • Additional Grounds: Petitioner asserted additional obviousness challenges. Claims 9 and 17-18 were challenged as obvious over Watanabe in view of Iizuka (Patent 5,250,465), arguing it was obvious to use known circular via shapes. Claims 45-47 were challenged as obvious over Watanabe in view of Kamoshima (Application # 2004/0173905), arguing for the obviousness of using branched interconnects to suppress microvoids. Further grounds combined Hasunuma with Kurashima, Aoyagi (Application # 2001/0019180) alone and with Hasunuma, Kunikiyo (Patent 6,717,267) alone and in combination with Iizuka and Watanabe, all based on similar theories of combining known semiconductor fabrication techniques for their predictable advantages.

4. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1-4, 7-9, 11-18, 21-22, 25-26, 28, 32, 39-40, 42, and 45-47 of Patent 7,439,623 as unpatentable.