Marvell Semiconductor Inc v. Credo Technology Group Ltd

1. Case Identification

• Case #: IPR2025-01220
• Patent #: 11,032,111
• Filed: August 8, 2025
• Petitioner(s): Marvell Semiconductor, Inc.
• Patent Owner(s): Credo Technology Group Ltd.
• Challenged Claims: 1-19

2. Patent Overview

• Title: Serial Communications Method
• Brief Description: The ’111 patent describes methods for high-speed serial communications that address channel attenuation by selecting initial pre-equalizer coefficient values from multiple sets stored in registers. These initial values, which correspond to different channel models, are subsequently refined using a link training process to optimize signal transmission.

3. Grounds for Unpatentability

Ground 1: Claims 1, 3-4, 6-8, 10-11, and 13-19 are obvious over Berke in view of Cornelius.

• Prior Art Relied Upon: Berke (Application # 2019/0288881) and Cornelius (Patent 8,516,238).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Berke taught the core inventive concept: a transceiver system that stores multiple sets of pre-equalizer coefficients in a "whitelist" of registers, selects an initial set corresponding to a particular channel model, and then updates those coefficients during a training phase to optimize performance. Berke's method explicitly uses performance metrics like eye diagrams and Bit Error Rate (BER) to select and refine the coefficients. Cornelius was cited for teaching a high-speed active cable with pluggable modules and transceivers at each end, providing the chip-to-module communication link environment recited in independent claims 8, 11, and 16.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Berke's equalization optimization techniques with Cornelius’s well-known active cable system to improve performance. Petitioner asserted this was a straightforward application of a known improvement method (Berke) to a standard device (Cornelius) to achieve predictable benefits in signal integrity for high-speed data transmission. Both references operate in the same technical field and apply to common standards like PCIe.
  • Expectation of Success: A POSITA would have had a high expectation of success because the combination involved applying Berke's known serial communication techniques to Cornelius's conventional serial links without changing the fundamental principles of operation of either reference.

Ground 2: Claims 1, 3-4, 6-8, 10-11, and 13-19 are obvious over Berke in view of Ran.

• Prior Art Relied Upon: Berke (Application # 2019/0288881) and Ran (Patent 10,715,357).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground relied on Berke for the same core teachings as Ground 1. Ran was substituted for Cornelius to provide the system context of a chip-to-module link. Ran taught a serial communication link between a host (e.g., a Network Interface Controller) and a hot-pluggable optical module. Ran further disclosed adapting a transmit equalizer using management registers to select from predefined equalization coefficient "presets," solving the same problem of optimizing equalization for varying conditions.
  • Motivation to Combine: Petitioner contended a POSITA would be motivated to apply Berke’s advanced method for selecting and optimizing coefficients to Ran’s system. Ran recognized the need for optimized equalization due to increasing data rates, and Berke provided an effective technique to achieve this. The combination was presented as a predictable pairing of a problem (need for better equalization in Ran) with a known solution (Berke's whitelist training method).
  • Expectation of Success: The teachings of Berke and Ran were argued to be readily compatible, as both address equalization in high-speed serial links for common standards. A POSITA would expect success in applying Berke's more detailed coefficient selection and training process to the system disclosed by Ran.

Ground 5: Claims 1-19 are obvious over Ran in view of Mejia and Stauffer.

• Prior Art Relied Upon: Ran (Patent 10,715,357), Mejia (Application # 2014/0237301), and Stauffer (a 2009 textbook on High Speed Serdes).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground asserted that Ran taught the foundational system: a chip-to-module link that selects from multiple "presets" of pre-equalizer coefficients and updates them during a training phase. Mejia was introduced to teach a specific "preset search" technique for how to select the best initial preset from multiple options by evaluating system performance against metrics like BER. Stauffer, a textbook, was cited to demonstrate that using registers to store equalization coefficients was a well-known, fundamental practice in the art and that channel models would inherently account for known signal degradation factors like "package loss" (recited in claims 2 and 9).
  • Motivation to Combine: A POSITA implementing Ran’s system, which requires selecting a preset, would have been motivated to use Mejia’s systematic preset search technique to find the optimal starting point, thereby improving the efficiency and outcome of the subsequent training. Stauffer’s teachings represented basic knowledge that a POSITA would naturally incorporate, such as using registers for storage (an obvious design choice for speed and simplicity) and considering all sources of signal loss, including package loss, when defining channel models.
  • Expectation of Success: The combination was argued to be obvious and predictable. Mejia provided a specific, known method to implement a function described more generally in Ran. Stauffer provided the foundational, common-knowledge details for building such a system.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on Berke, Cornelius, and Stauffer (Ground 3) and Berke, Ran, and Stauffer (Ground 4). These grounds added the Stauffer textbook to Grounds 1 and 2, respectively, to explicitly teach dependent claim limitations regarding channel models that account for insertion loss and package loss characteristics.

4. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-19 of Patent 11,032,111 as unpatentable under 35 U.S.C. §103.