PTAB

IPR2025-01265

Taiwan Semiconductor Mfg Co Ltd v. Marlin Semiconductor Ltd

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device And Fabrication Method Thereof
  • Brief Description: The ’384 patent discloses a fabrication method for FinFET transistors. The method involves forming a fin structure protruding from a substrate, an isolation structure surrounding the fin, a gate structure overlaying the fin, and an epitaxial structure. The key inventive concept asserts a method where, after forming the gate, a recess is formed in the fin and the isolation structure is etched, such that the bottom surface of the fin recess has a depth greater than the etched top surface of the isolation structure.

3. Grounds for Unpatentability

Ground 1: Claims 1-9 are obvious over Xu in view of the knowledge of a POSITA.

  • Prior Art Relied Upon: Xu (Patent 9,166,022).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Xu, which describes FinFET fabrication, discloses all limitations of the challenged claims across two adjacent embodiments. Xu’s first embodiment was asserted to teach forming a fin, an isolation structure, and a gate, and then etching the isolation structure after the gate is formed. Xu's second embodiment was asserted to teach a process of forming recesses in the fin structure at the sides of the gate to create strain for improved performance. Petitioner contended that combining these steps meets all limitations of independent claim 1. Specifically, when the fin-recessing step of the second embodiment is applied to the first, the resulting structure would have a recess bottom depth (second depth) that is necessarily deeper than the etched isolation structure's top surface (first depth), meeting limitation 1[g]. For dependent claims, Petitioner argued Xu also teaches using a shallow trench isolation (STI) structure (claim 2), employing wet or dry etching (claims 3 and 5), forming the epitaxial layer from silicon germanium (SiGe) or silicon phosphide (SiP) (claim 6), and forming spacers on the gate sidewalls before etching the isolation structure (claims 7-8). Regarding claim 9’s replacement metal gate (RMG) process steps, Petitioner argued a POSITA would understand Xu’s disclosure of a “gate-last” process to inherently include these well-known techniques.
    • Motivation to Combine (for §103 grounds): A POSITA would combine the fin-recessing step from Xu's second embodiment with its first embodiment to gain the known benefits of strained source/drain features, which enhance carrier mobility and device performance. Petitioner asserted that Xu itself suggests this combination by summarizing the invention to include both steps and by claiming a method combining both steps in its own dependent claim 19.
    • Expectation of Success (for §103 grounds): Petitioner argued a POSITA would have had a reasonable expectation of success because Xu discloses conventional etching processes that could be readily applied to the fins of the first embodiment to predictably control recess depth and achieve the desired strain characteristics.

Ground 2: Claims 4 and 9 are obvious over Lin in view of Brask.

  • Prior Art Relied Upon: Lin (Application # 2012/0091538) and Brask (Application # 2005/0148137).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner characterized Lin as disclosing a complete "gate-first" FinFET fabrication process. However, to address claims 4 (dummy gate) and 9 (RMG process), Petitioner proposed modifying Lin with the teachings of Brask. Brask was presented as teaching a well-established "gate-last" (or RMG) process using a sacrificial, or "dummy," gate. Petitioner argued the combination involves replacing Lin's gate-first formation step with Brask's gate-last process. This substitution would introduce a "dummy gate structure" as required by claim 4. It would also teach the full sequence of claim 9: depositing an interlayer dielectric to surround the dummy gate (shown in Brask Fig. 6H), removing the dummy gate to leave a trench (Fig. 6I), conformally forming a new gate dielectric layer in the trench (Fig. 6J), and forming a conductive layer to fill the trench (Fig. 6J), thereby creating the final operative gate.
    • Motivation to Combine (for §103 grounds): Petitioner argued that by the ’384 patent's priority date, there was a known industry-wide shift away from "gate-first" processes like Lin's toward "gate-last" processes like Brask's. The primary motivation was to avoid thermal degradation of the gate structure, which occurs in gate-first processes when the gate is exposed to high-temperature annealing. Adopting Brask's gate-last approach would predictably solve this known problem and allow for better control over the final gate’s work function, an advantage explicitly touted by Brask.
    • Expectation of Success (for §103 grounds): A POSITA would have expected success because substituting a well-known gate-last process for a gate-first process was a common and understood technique for improving FinFET performance. The combination was presented as the application of a known solution (Brask) to a known problem in a known device (Lin), yielding predictable results.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1-3 and 5-8 are obvious over Lin in view of POSITA knowledge (Ground 2A), and that claims 4 and 9 are obvious over Xu in view of Brask (Ground 1B).

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9 of the ’384 patent as unpatentable.