PTAB

IPR2025-01266

Samsung Electronics Co Ltd v. Radian Memory Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Systems and methods for flash memory controller
  • Brief Description: The ’183 patent relates to a flash memory controller for a system where memory is organized into units termed "subdivisions." The controller tracks metadata, such as page utilization and erase counts for each subdivision, and provides this metadata to a host system for use in cooperative memory management.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 8, 10-14, 18, and 20 are obvious over Ellis in view of Son.

  • Prior Art Relied Upon: Ellis (Patent 9,239,781) and Son (Application # 2012/0096217).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ellis discloses the foundational elements of the challenged claims, including a flash memory controller that manages memory organized into "superblocks" (the claimed "subdivisions") and tracks metadata such as a "valid-page count" (the claimed "page utilization"). Ellis also teaches that memory management responsibility can be shared between the controller and a host. Son further teaches a cooperative management system using superblocks and storing metadata like "wear count" and "valid page count" in a "Superblock Table" that a host can access.
    • Motivation to Combine: A POSITA would combine the references because they are in the same field of NAND flash memory management, address the same problems of performance and longevity, and use analogous techniques. Petitioner asserted a POSITA would be motivated to incorporate Son’s more detailed metadata tracking (e.g., wear counts) and explicit host-querying functionality into Ellis’s base system to enhance its cooperative management capabilities. Ellis also explicitly cites to Son.
    • Expectation of Success: Petitioner contended that adding known types of metadata to an existing memory management system and implementing a host-query function would be a routine, predictable modification with a high expectation of success.

Ground 2: Claims 6, 9, 17, and 19 are obvious over Ellis in view of Son and Yamada.

  • Prior Art Relied Upon: Ellis (Patent 9,239,781), Son (Application # 2012/0096217), and Yamada (Application # 2011/0271032).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the Ellis/Son combination to address claims requiring the tracking of time-based metadata and comparison to a threshold. Petitioner argued Ellis teaches copying "older" blocks, and Son explicitly teaches tracking "last modification time." Yamada was introduced to teach a controller that identifies blocks needing maintenance based on "elapsed time" compared against a "criterion value" (a threshold) and then transmits a maintenance request to the host, which in turn issues the copy command.
    • Motivation to Combine: A POSITA would add Yamada's specific controller-initiated, host-commanded maintenance protocol to the shared-responsibility framework of Ellis and Son. This combination would provide the known benefits of offloading maintenance scheduling from the resource-constrained controller to the more powerful host, which is a known design choice in the art.
    • Expectation of Success: Petitioner argued the combination was predictable because Yamada provides a discrete, detailed embodiment of the general shared host-controller responsibility already taught by Ellis and Son, making its integration straightforward.

Ground 3: Claims 1, 2, 8, 10-14, 18, and 20 are obvious over Sinclair in view of Yu and Son.

  • Prior Art Relied Upon: Sinclair (Patent 7,739,444), Yu (Application # 2012/0284587), and Son (Application # 2012/0096217).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presents an alternative combination where Sinclair provides the base system. Petitioner asserted Sinclair teaches a controller managing flash memory organized into "metablocks" (subdivisions) and tracking metadata like "pages of unprogrammed capacity" (page utilization). Similar to Ground 1, Son was added to provide more detail on metadata tracking and host interaction. Yu was added to teach a specific, well-known mechanism for this interaction, disclosing that a host can use S.M.A.R.T. commands to query a controller for metadata including "wear-leveling count" and "block status."
    • Motivation to Combine: A POSITA would combine Sinclair and Son due to their analogous teachings on memory organization and metadata-based management. Yu would be incorporated to implement the host-querying functionality using a well-known industry standard (S.M.A.R.T.), providing a concrete and reliable method to achieve the shared management contemplated by Sinclair.
    • Expectation of Success: Petitioner contended that incorporating a standard protocol like S.M.A.R.T. into a system already designed for shared host-controller responsibility would be a routine modification for a skilled artisan.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 6, 9, 17, and 19 based on the combination of Sinclair, Yu, Son, and Jung. This ground added Jung's teachings on cooperative memory management to provide further support for a host performing functions based on metadata loaded from the controller.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 2, 6, 8-14, and 17-20 of the ’183 patent as unpatentable.