PTAB

IPR2025-01283

SanDisk Corp v. Longitude Flash Memory Solutions Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Non-Volatile Memory Device
  • Brief Description: The ’240 patent relates to improving data retention capabilities in non-volatile silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The invention discloses using a multi-layer charge-trapping region, specifically an "oxide-nitride-nitride-oxide (ONNO) stack," which can be implemented in either horizontal or vertical three-dimensional (3D) transistor structures.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lee ’255, Lee ’961, and Fujiwara - Claims 1, 3-7, 9, and 11 are obvious over Lee ’255 in view of Lee ’961 and Fujiwara.

  • Prior Art Relied Upon: Lee ’255 (Application # 2012/0068255), Lee ’961 (Korean Patent Publication No. 2011-0118961), and Fujiwara (Application # 2006/0065919).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Lee ’255 teaches a foundational 3D vertical SONOS memory device including a gate structure, vertical channel, and a standard oxide-nitride-oxide (ONO) stack. To address known data retention issues like charge leakage in such devices, Lee ’961 teaches replacing the single nitride charge trapping layer with a multi-layer structure comprising two nitride layers separated by an oxide “anti-tunneling layer” (an ONONO configuration). Petitioner further argued that Fujiwara teaches optimizing this multi-layer nitride structure by using an “oxygen-rich” nitride layer and an “oxygen-lean” nitride layer to further improve charge retention characteristics. The combination of these references allegedly discloses every limitation of the challenged claims.
    • Motivation to Combine: A POSITA would combine Lee ’255 with Lee ’961 because Lee ’961 expressly teaches using a multi-layer charge trap to solve the known problem of poor charge retention in 3D memory devices like those in Lee ’255. A POSITA would be further motivated to incorporate Fujiwara’s teachings because optimizing oxygen concentrations in nitride layers was a known method to predictably enhance data retention, directly aligning with the goals of Lee ’255 and Lee ’961.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because all three references address analogous 3D charge trap memory structures. The proposed modifications involved combining known elements (multi-layer traps, optimized oxygen concentrations) using conventional fabrication techniques to achieve the predictable result of improved data retention.

Ground 2: Obviousness over Lee ’255, Lee ’961, Fujiwara, and Hwang - Claims 12-18 are obvious over the combination of Lee ’255, Lee ’961, and Fujiwara in view of Hwang.

  • Prior Art Relied Upon: Lee ’255 (Application # 2012/0068255), Lee ’961 (Korean Patent Publication No. 2011-0118961), Fujiwara (Application # 2006/0065919), and Hwang (Application # 2012/0061744).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the memory device structure established in Ground 1. Petitioner argued that claims 12 and 16 add the limitation of a metal oxide semiconductor (MOS) logic device connected to the memory device. Hwang was introduced to teach this element, as it explicitly discloses peripheral MOS logic transistors for controlling the operation of 3D NAND memory devices that are structurally similar to the device in Lee ’255. Hwang allegedly teaches the MOS logic device including a gate oxide layer and a high work function gate electrode, as required by the claims.
    • Motivation to Combine: A POSITA would combine Hwang’s teachings with the memory device from Ground 1 because peripheral MOS logic devices were conventional and necessary components for controlling any NAND flash memory architecture. Incorporating Hwang's peripheral logic circuit was an obvious and routine design choice to create a functional device, with the express benefits of simplified fabrication and improved reliability.
    • Expectation of Success: Success was expected because integrating peripheral control logic with memory arrays was a standard industry practice. The device architectures disclosed in Lee ’255 and Hwang were common and compatible, and the combination required only the application of well-established 3D NAND connection techniques without any new materials or unconventional process steps.

4. Key Claim Construction Positions

  • “oxygen-rich nitride” and “oxygen-lean nitride”: Petitioner argued that based on an example in the ’240 patent specification, a POSITA would understand “oxygen-rich” to mean a nitride layer with an oxygen concentration of about 15% to 40% and “oxygen-lean” to mean a concentration of less than about 5%.
  • “high work function gate electrode”: Petitioner contended this term should be given its plain and ordinary meaning, which was well-known to a POSITA and includes materials such as polysilicon doped with p-type impurities.
  • “semiconductor material structure”: Petitioner argued that based on the ’240 patent’s claims and prosecution history of a related patent, a POSITA would understand this term to be synonymous with “semiconductor substrate.”

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3-7, 9, and 11-18 of the ’240 patent as unpatentable under 35 U.S.C. §103.