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IPR2025-01305

Taiwan Semiconductor Mfg Co Ltd v. Advanced Integrated Circuit Process LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Fabricating a Semiconductor Device
  • Brief Description: The ’572 patent relates to a method for fabricating semiconductor devices with multi-layer interconnects. The claimed method involves forming an interconnect layer, covering it with an oxidation-resistant conductor film, depositing second and third insulating films, and then etching through both insulating films in a single step to expose the oxidation-resistant film.

3. Grounds for Unpatentability

Ground 1: Obviousness over Parikh in view of Komada - Claims 1-7 are obvious over Parikh in view of Komada

  • Prior Art Relied Upon: Parikh (Application # 2003/0148618) and Komada (Japan Patent # JP20020289689).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Parikh disclosed a nearly identical semiconductor fabrication method, including forming a conductive element on a substrate, depositing a metal passivation layer (e.g., titanium nitride), depositing second and third dielectric layers, and forming vias by etching through both dielectric layers until the metal passivation layer was exposed. Petitioner contended that this passivation layer was inherently an oxidation-resistant conductor film as claimed. For claims 4, 6, and 7, Petitioner asserted Komada supplied the teaching of forming separate interconnect structures, such as a core circuit region and a peripheral moisture-resistant ring, and etching trenches and holes concurrently.
    • Motivation to Combine (for §103 grounds): Petitioner argued a person of ordinary skill in the art (POSITA) would combine Parikh and Komada because both addressed the problem of protecting copper interconnects during fabrication. A POSITA would have incorporated Komada's teaching of a moisture-resistant ring trench around Parikh’s core region to predictably improve device reliability by preventing moisture ingress, a known technique to improve similar multi-layer semiconductor structures.
    • Expectation of Success (for §103 grounds): A POSITA would have had an expectation of success because both references described compatible materials (e.g., copper, TiN) and standard damascene process steps, yielding predictable results like improved etch selectivity and enhanced reliability.

Ground 2: Obviousness over Roberts, alone or in view of Parikh - Claims 1-3 and 5 are obvious over Roberts, alone or in view of Parikh

  • Prior Art Relied Upon: Roberts (Patent 6,461,914) and Parikh (Application # 2003/0148618).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Roberts disclosed all steps of claim 1 for fabricating a metal-insulator-metal capacitor, including forming an interconnect layer (a first metal layer), a conductive oxidation barrier layer (e.g., titanium nitride), a second insulating film (capacitor dielectric layer), and a third insulating film (ILD layer). Roberts further taught using a photoresist mask to etch through both insulating layers to expose the underlying barrier layer. Petitioner asserted that Roberts disclosed this etching could occur in a single step within the same chamber.
    • Motivation to Combine (for §103 grounds): To the extent Roberts was found not to explicitly teach a one-step etch, Petitioner argued a POSITA would have been motivated to apply Parikh’s explicit one-step etching process to Roberts' fabrication method. This combination would simplify the process, increase throughput, and reduce costs by eliminating etch stop layers, which was a known technique to improve similar damascene structures.
    • Expectation of Success (for §103 grounds): A POSITA would have expected success because both references used compatible materials and processes for copper metallization. The combination involved applying a known, more efficient etching technique (from Parikh) to a standard multi-layer structure (in Roberts) to achieve a predictable improvement in manufacturing efficiency.

Ground 3: Obviousness over Parikh, Komada, and Maeda - Claim 2 is obvious over Parikh, Komada, and Maeda

  • Prior Art Relied Upon: Parikh (Application # 2003/0148618), Komada (Japan Patent # JP20020289689), and Maeda (Japan Patent Publication # JPH1116906A).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Parikh and Komada from Ground 1, adding Maeda to address the "plasma treatment" limitation of claim 2. Petitioner argued Maeda explicitly taught forming an antioxidant film on an interconnect layer by irradiating its surface with a nitrogen-containing plasma to introduce nitrogen into its upper portion. Parikh already taught that the oxidation-resistant layer could be formed using PVD, a type of plasma treatment.
    • Motivation to Combine (for §103 grounds): Petitioner argued a POSITA would combine Maeda with the Parikh/Komada framework because all three references focused on protecting metal interconnects from oxidation. A POSITA would have applied Maeda’s plasma treatment as a known, low-temperature method to form the oxidation-resistant layer in Parikh’s process, thereby improving the reliability of the copper interconnects in a predictable manner.
    • Expectation of Success (for §103 grounds): Success was expected because nitrogen plasma treatment was a well-established, straightforward technique in semiconductor fabrication compatible with the damascene flows and materials described in Parikh and Komada, predictably yielding a robust protective layer.
  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 2 is obvious over Roberts, Parikh, and Maeda, and that claims 4-7 are obvious over Roberts, Parikh, and Komada. These grounds relied on similar rationales of applying known techniques from one reference to improve the processes of another.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-7 of Patent 8,329,572 as unpatentable.