BOE Technology Group Co Ltd v. Bishop Display Tech LLC

1. Case Identification

• Case #: IPR2025-01330
• Patent #: 7,995,047
• Filed: July 28, 2025
• Petitioner(s): BOE Technology Group Co., Ltd.
• Patent Owner(s): Bishop Display Tech LLC
• Challenged Claims: 1-10

2. Patent Overview

• Title: Current Driving Device
• Brief Description: The ’047 patent discloses a current driving device for displays, such as OLEDs. The device operates using three distinct modes—a voltage supply mode, a current supply mode, and a current output mode—intended to charge a voltage holding circuit at high speed to drive display pixels.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Baek - Claims 1-4 and 9 are anticipated by, or at least obvious over, Baek.

• Prior Art Relied Upon: Baek (Application # 2006/0170629).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Baek discloses a display driver circuit with current sample/hold circuits that operate in three modes corresponding to those claimed. Baek’s “pre-charge circuit 350” is the claimed “first voltage supply source” supplying a “first voltage.” Its “current digital-to-analog conversion unit 330” is the “first current supply source” supplying a “first electric current.” The current output circuits in Baek (e.g., circuit 370-k) each contain the elements of claim 1(d)(2): a current-voltage converting circuit (transistor M1 and switches S1/S2 charging capacitor CST), a voltage-current converting circuit (transistor M2 converting voltage on CST to an output current), and a voltage holding circuit (storage capacitor CST). Petitioner contended that during its current charge mode, the reference voltage on the terminal of capacitor CST is different from the pre-charge voltage supplied in the voltage supply mode, meeting a key limitation added during prosecution.
  • Key Aspects: Petitioner asserted that Baek’s circuit operates sequentially through a pre-charge mode (voltage supply), a current supply mode (charging the capacitor with analog gray-scale current), and a current output mode, directly mapping to the functionalities claimed in the ’047 patent.

Ground 2: Obviousness over Baek and Date - Claims 5-6 are obvious over Baek in view of Date.

• Prior Art Relied Upon: Baek (Application # 2006/0170629), Date (Application # 2005/0231241).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that while Baek provides the base circuit of claim 1, Date teaches the additional elements of claim 5. Specifically, Date discloses a display driver with a second current supply source (p-transistor 1423 in a current mirror with p-transistor 1421) that supplies a proportional second electric current. Date also teaches a second current-voltage converting circuit (n-transistor 1422) that generates a gate voltage based on this second current, which is then used to control the current output circuits.
  • Motivation to Combine: A POSITA would combine Date’s bias circuit teachings with Baek’s driver circuit to enhance reliability and simplify the design. Baek does not specify the implementation of its pre-charge circuit 350. A POSITA would look to known solutions like Date’s current mirror-based voltage generator to provide a constant, reliable pre-charge voltage derived from a reference current. This would advantageously use the existing analog gray-scale current from Baek’s DAC as a reference, simplifying the overall circuitry.
  • Expectation of Success: A POSITA would have a reasonable expectation of success, as the combination involves applying a well-known current mirror and voltage generation circuit (from Date) to a standard display driver architecture (from Baek) for the predictable purpose of creating a stable voltage source.

Ground 3: Obviousness over Sasaki - Claim 10 is obvious over Sasaki.

• Prior Art Relied Upon: Sasaki (Application # 2005/0017765).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Sasaki discloses a current generation supply circuit that renders claim 10 obvious. Sasaki’s “current supply source control transistor TP36” is the claimed “current input switch” controlling connection to a “constant current generation source IRA” (the current supply source). The “capacitor Ca” is the “voltage holding circuit” charged by a flown current (“reference current Iref”). Sasaki’s “refresh control transistor Tr10” or, alternatively, “reference current transistor TP11” serves as the “calibration switch.” The “plurality of module current transistors TP12-TP15” are the claimed “plurality of voltage-current converting elements” that generate current based on the voltage held in capacitor Ca. The “switching transistors TP16-TP19” are the “plurality of signal response switches” connected in series with the module transistors.
  • Key Aspects: Petitioner contended that Sasaki’s circuit provides a detailed schematic where each element of claim 10 can be identified. The connection node is the “current input contact INA,” and the current output switches are the “output control transistor Tr311” and “Pch FET Tr42,” which are interposed between the connection node and the final current output terminals. Sasaki also teaches a high-speed switch (Tr10) that controls the connection of a voltage supply (+V) to a terminal of the voltage holding circuit (capacitor Ca), meeting the final limitation of claim 10.

4. Arguments Regarding Discretionary Denial

• §325(d) Arguments: Petitioner argued that discretionary denial under §325(d) is inappropriate because the core prior art references asserted in the petition—namely Baek, Inomoto, and Sasaki—were never considered by the examiner during the original prosecution of the ’047 patent. Petitioner contended that even though Date was previously cited, it was not presented in the current combination with Baek, and the arguments are substantially different.
• §314(a) Fintiv Arguments: Petitioner asserted that the Fintiv factors weigh in favor of institution. The co-pending district court litigation has a trial date scheduled for January 11, 2027, which is far in the future and will likely coincide with or follow a Final Written Decision in this IPR. Investment in the district court case is minimal, with only a case schedule set. Further, Petitioner stipulated that if the IPR is instituted, it will not pursue the same invalidity grounds in the district court litigation.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’047 patent as unpatentable under 35 U.S.C. §102 and/or §103.