PTAB

IPR2025-01376

Samsung Electronics Co Ltd v. Radian Memory Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Hierarchical Address Virtualization for Flash Memory
  • Brief Description: The ’995 patent discloses a logical-to-physical address translation system for a flash memory storage device. The system uses a memory controller to receive commands and translate hierarchical logical addresses from a host into physical sub-addresses for managing the underlying flash memory structure.

3. Grounds for Unpatentability

Ground 1: Obviousness over Reiter, ZBC, SBC-4, SPC-4, and Sinclair-367 - Claims 1-5, 7-11, 13-15, 18-20, 26-30 are obvious over the combination of these references.

  • Prior Art Relied Upon: Reiter (Patent 8,301,861), ZBC (a T10 SCSI working draft), SBC-4 (a T10 SCSI working draft), SPC-4 (a T10 SCSI working draft), and Sinclair-367 (Application # 2005/0144367).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Reiter taught the foundational flash memory system with a controller that performs logical-to-physical address translation. Reiter’s hierarchical addressing scheme, which breaks a logical block address (LBA) into superblocks, block numbers, and page numbers, provides the basic framework. The combination of ZBC, SBC-4, and SPC-4—industry standard SCSI command specifications—was argued to teach the use of zoned block devices, which are analogous to Reiter’s superblocks. Petitioner asserted that these standards disclose the commands for identifying logical units (block devices) and zones (segments) within them. Sinclair-367 was argued to add teachings on key maintenance and performance features, including maintaining metadata for each physical erase unit (e.g., "time since data was programmed" and erase counts for wear-leveling) and using multi-plane architectures with "metablocks" to perform concurrent operations for improved parallelism. Petitioner mapped how Reiter’s use of division to derive address portions (e.g., logical block number from a logical sector number) meets the "division operation" limitation of claim 1.
    • Motivation to Combine: Petitioner contended a POSITA would combine these references for predictable reasons. A POSITA would integrate the ZBC/SBC/SPC standards with Reiter’s flash system to improve interoperability using widely adopted SCSI protocols, noting the direct analogy between Reiter's "superblocks" and ZBC's "zones." A POSITA would then incorporate Sinclair-367’s teachings to enhance the combined system's performance and longevity—well-known goals in the field—by implementing parallel operations across multiple memory planes and adding robust wear-leveling and data retention management based on metadata.
    • Expectation of Success: Petitioner asserted a POSITA would have had a reasonable expectation of success because all references were in the analogous art of storage devices. SCSI standards were designed for broad use, including flash memory, and ZBC's zoned block model was a logical construct that could be layered onto any storage device like Reiter’s.

Ground 2: Obviousness over Reiter, ZBC, Sinclair-367, and Yamada - Claims 6 and 21 are obvious over the combination of these references.

  • Prior Art Relied Upon: Reiter (Patent 8,301,861), ZBC (a T10 SCSI working draft), Sinclair-367 (Application # 2005/0144367), and Yamada (Application # 2011/0271032).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1, adding Yamada to address the specific limitations of claims 6 and 21. These claims required circuitry to compare metadata to a threshold and, in response, transmit information to a host that conveys address information for the associated data. Petitioner argued that Yamada disclosed this exact scheme to solve the known problem of maintenance operations (like garbage collection) degrading system performance, a problem explicitly mentioned in Reiter. Yamada taught a maintenance request unit in the memory controller that compares data status (metadata) against a criterion value (threshold) and, upon exceedance, transmits a maintenance request with a logical address to the host. The host then uses this information to schedule maintenance, such as copying data from an aging block, which is dependent on the transmitted information.
    • Motivation to Combine: The motivation to add Yamada to the primary combination was to solve a known problem identified in the primary reference, Reiter. A POSITA, facing the performance degradation from garbage collection described by Reiter, would have been motivated to incorporate Yamada's maintenance scheme, which was designed to perform such operations during lulls in system processing, thereby improving overall performance.
    • Expectation of Success: Petitioner argued success would be expected because Yamada provided a clear solution to a well-understood problem in flash memory management.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-11, 13-15, 18-21, 26-30 of the ’995 patent as unpatentable.