PTAB

IPR2025-01378

Samsung Electronics Co Ltd v. Radian Memory Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Flash Memory Controller with Hierarchical Address Virtualization
  • Brief Description: The ’657 patent discloses systems and methods for a flash memory controller that performs logical-to-physical address translation. The technology purports to achieve negligible translation time by using "hierarchal address virtualization," where a logical address is translated into virtual sub-addresses that correspond to physical memory structures.

3. Grounds for Unpatentability

Ground I: Obviousness over Reiter, ZBC, SBC-4, and SPC-4 - Claims 1-4, 6-9, 13, 15, and 19-22 are obvious over Reiter in view of the T10 Standards.

  • Prior Art Relied Upon: Reiter (Patent 8,301,861), and three SCSI working drafts: Zoned Block Commands (“ZBC”), SCSI Block Commands – 4 (“SBC-4”), and SCSI Primary Commands – 4 (“SPC-4”) (collectively "T10 Standards").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Reiter taught a flash memory system with a controller that performs logical-to-physical address translation. Reiter's controller receives requests with a Logical Block Address (LBA) and translates it into a superblock number, block index, and page index. Petitioner contended this maps to the core structure of claim 1. The T10 Standards, particularly the ZBC command set, were argued to supply the claimed write and erase requests. The ZBC "reset write pointer" command, which makes data in a zone inaccessible, was asserted to be an erase request. Petitioner mapped the claimed "first division operation" and "second division operation" to Reiter's method of deriving the superblock number and block/page index from an LBA using integer division.
    • Motivation to Combine: A POSITA would combine Reiter with the T10 Standards because Reiter expressly disclosed support for widely used SCSI protocols. ZBC's "zones" were argued to be analogous to Reiter's "superblocks," making the command set a natural fit to enable more effective and interoperable utilization of Reiter’s memory organization scheme. All three T10 Standards are designed to be used together.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because SCSI protocols were widely known, familiar, and intended for use with flash memory devices. Petitioner asserted that Reiter’s superblock organization was well-suited for ZBC’s zone-based commands and that the ZBC logical model could be layered on top of any storage device.

Ground II: Obviousness over Reiter, T10 Standards, and Sinclair-367 - Claims 5, 10-13, and 18 are obvious over the combination of Ground I and Sinclair-367.

  • Prior Art Relied Upon: Reiter (Patent 8,301,861), ZBC, SBC-4, SPC-4, and Sinclair-367 (Application # 2005/0144367).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground added Sinclair-367 to the combination from Ground I to teach limitations related to bad block management and metadata storage. Petitioner argued Sinclair-367 disclosed storing metadata, such as "time of programming" or program/erase cycle counts, in each erase unit. This was mapped to claim 10’s requirement to store a value representing time since data was programmed and compare it to a threshold. Sinclair-367’s disclosure of remapping a logical address from a defective block to a substitute block was argued to meet claim 13’s limitations regarding detecting a failure condition and remapping the logical erase unit. Sinclair-367 also taught organizing memory into multiple planes to increase parallelism, mapping to claim 18.
    • Motivation to Combine: A POSITA would be motivated to incorporate Sinclair-367’s teachings into the Reiter/T10 system to improve system resiliency and prolong the lifespan of the flash memory. Since Reiter already contemplated bad block management, implementing the specific methods from Sinclair-367 would be a predictable improvement.

Ground IV: Obviousness over Sinclair-233 - Claims 1-2, 8-9, and 18-22 are obvious over Sinclair-233.

  • Prior Art Relied Upon: Sinclair-233 (Patent 7,984,233).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued Sinclair-233 alone taught all limitations of the challenged claims. Sinclair-233 disclosed a flash memory system with a "direct file interface" where incoming requests use a full pathname (including a storage ID and directory hierarchy) as address information. Petitioner mapped the claimed derivation of a "first address portion" and "second address portion" to parsing this pathname. The storage ID was identified as the first portion (identifying the "addressed block device"), and the directory/file path was the second portion. The "first division operation" was mapped to using a delimiter (e.g., '') to parse the pathname to identify a filename (the "addressed segment"). The "second division operation" was mapped to using integer division on a File Index Table entry to extract a block number and byte number, which select an erase unit and storage location.

  • Additional Grounds: Petitioner asserted Ground III, which argued claims 14 and 16-17 are obvious over the combination of Reiter, the T10 Standards, and Yamada (Application # 2011/0271032). This ground relied on Yamada to teach transmitting maintenance requests from the storage device to the host to reduce processing delays.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-22 of the ’657 patent as unpatentable.