PTAB

IPR2025-01402

Samsung Semiconductor Inc v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Package Having Stacked Array Dies
  • Brief Description: The ’087 patent relates to a dynamic random access memory (DRAM) package with stacked memory dies. The technology purports to improve upon prior art by using a control die with multiple conduits (e.g., drivers) coupled to a single data terminal, where each conduit drives signals through a separate die interconnect to a distinct subset of the stacked DRAM dies, thereby reducing the electrical load on each individual driver.

3. Grounds for Unpatentability

Ground 1: Claims 1-28 are obvious over Keeth in view of Shaeffer

  • Prior Art Relied Upon: Keeth (Patent 9,123,552) and Shaeffer (Patent 9,665,507).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Keeth disclosed the core architecture of the challenged claims, including a DRAM package with a stack of memory dice coupled to a control/interface die. Keeth’s architecture used interleaving conductive paths to connect the interface die to alternating (e.g., odd and even) dice in the stack. Petitioner contended that while Keeth provided the physical structure, it lacked a detailed signaling protocol. Shaeffer allegedly supplied this missing element by teaching a high-speed signaling protocol for communication between a memory controller and memory devices, including the use of separate interconnects for command/address (C/A) signals and data signals to increase bandwidth. The combination of Keeth’s stacked architecture with Shaeffer’s signaling protocol allegedly rendered the claimed invention obvious.
    • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSITA) would combine these references to achieve a predictable improvement. A POSITA looking to implement Keeth’s stacked memory architecture, which aims to increase bandwidth, would have been motivated to incorporate the advantageous and well-known high-speed signaling protocols taught by Shaeffer. Using separate C/A and data lines, as taught by Shaeffer and standardized in DDR3 SDRAM (which Keeth explicitly mentions), was a known method for improving data throughput, a goal consistent with Keeth’s invention.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in combining Keeth’s memory stack with Shaeffer’s signaling protocols. Both references related to stacked memory devices, and implementing a known signaling standard within a compatible hardware architecture was a routine design choice intended to achieve the predictable result of increased performance.

Ground 2: Claims 1-28 are obvious over Keeth and Shaeffer in view of Riho2

  • Prior Art Relied Upon: Keeth (Patent 9,123,552), Shaeffer (Patent 9,665,507), and Riho2 (Application # 2010/0195364).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Keeth and Shaeffer by adding the teachings of Riho2 to address claim limitations related to varying driver sizes. Petitioner argued that in the Keeth-Shaeffer combination, the interleaving conductive paths would have different lengths depending on which die they connected to, resulting in different parasitic capacitance and resistance loads. Riho2 directly addressed this known issue in stacked chips by teaching the optimization of output driver capacity (i.e., driver size) to account for changes in the time constant caused by such parasitic effects. Riho2’s disclosure of using drivers of different sizes to match different loads allegedly taught the limitations of claims requiring, for example, a first driver of a first size and a second driver of a different, second size.
    • Motivation to Combine: A POSITA implementing the Keeth-Shaeffer combination would recognize that varying conductive path lengths create inconsistent signal timing and integrity issues, particularly at high frequencies. Petitioner contended a POSITA would be motivated to consult a reference like Riho2, which explicitly solved this problem by optimizing driver sizes. Applying Riho2’s teachings would predictably improve and stabilize memory operations, reduce power consumption, and increase manufacturing yield, providing a strong motivation for its inclusion.
    • Expectation of Success: Petitioner argued that implementing Riho2’s driver-size optimization was well within the skill of a POSITA. The problem of varying loads in stacked memory was known, and Riho2 provided a clear solution. A POSITA would have a reasonable expectation of success in applying this known optimization technique to the predictable electrical characteristics of the Keeth-Shaeffer combination using standard design tools.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-28 of Patent 12,308,087 as unpatentable.