PTAB

IPR2025-01451

SK Hynix Inc v. Advanced Memory Technologies LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Internal Voltage Generating Circuit
  • Brief Description: The ’231 patent discloses an internal voltage generating circuit, such as those used in memory devices, that employs two boost circuits (charge pumps) connected serially. The alleged novelty resides in using a frequency dividing circuit and a buffer circuit to supply the second boost circuit with a clock signal that is selectable between an original frequency and a divided frequency.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kishimoto in view of Abe - Claims 1, 3, 4, and 6-8 are obvious over Kishimoto in view of Abe.

  • Prior Art Relied Upon: Kishimoto (Patent 6,473,321) and Abe (Patent 8,102,157).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kishimoto discloses the core architecture of the ’231 patent, including an internal voltage generating circuit with two serially connected charge pumps (CP10 and CP20), a frequency divider (51), and a switching circuit (52) that supplies a clock signal to the second charge pump. However, Kishimoto’s switching circuit selects between two different divided clock signals (CLK1, CLK2). The challenged claims require a buffer circuit that selects between the original clock signal and a divided clock signal. Petitioner contended Abe supplies this missing element, as it explicitly discloses a selector circuit that can choose between an original clock signal and one or more divided clock signals.
    • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSITA) would combine Kishimoto and Abe because both relate to internal voltage generating circuits and address the known design goal of providing flexible clock frequencies to charge pumps. A POSITA would have looked to Abe’s selector design to improve the flexibility of Kishimoto’s circuit, which already aimed to vary clock frequency to improve performance and reliability.
    • Expectation of Success: A POSITA would have had a high expectation of success because implementing Abe’s selector logic into Kishimoto’s circuit was a predictable design choice involving the routine combination of well-understood circuit components (multiplexers and frequency dividers).

Ground 2: Obviousness over Abe - Claims 1, 3, 4, and 6-8 are obvious over Abe.

  • Prior Art Relied Upon: Abe (Patent 8,102,157).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Abe alone renders the claims obvious. Abe discloses a multi-output power supply device with a first power supply circuit serially connected to a second power supply circuit (fulfilling the two boost circuit limitations), a division circuit, and a selector circuit. However, in Abe’s primary embodiment (Fig. 1), the signal supplied to the first boost circuit (a triangular wave, TW) is different from the signal supplied to the frequency divider (a rectangular wave, SQW). Petitioner argued it would have been obvious to modify Abe’s circuit to use the same triangular wave signal (TW) as the input for both the first boost circuit and the frequency divider.
    • Motivation to Combine: The motivation was said to come from Abe itself, which teaches in a second embodiment (Fig. 2) that the oscillation circuit can generate only the triangular wave signal. A POSITA would have been motivated by this teaching to simplify the primary embodiment’s circuitry by eliminating the need to generate a separate rectangular wave signal.
    • Expectation of Success: Success would have been reasonably expected, as the modification involved a minor simplification taught within the same reference to achieve a more efficient circuit design.

Ground 3: Anticipation by Hiiragizawa - Claims 3, 4, and 6-8 are anticipated by Hiiragizawa.

  • Prior Art Relied Upon: Hiiragizawa (Patent 5,941,990).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Hiiragizawa discloses every limitation of the challenged claims. Hiiragizawa teaches a charge pump circuit that includes a frequency division circuit (6x) and a switching circuit (7). The switching circuit selects between an original clock signal (CK) and a divided clock signal (DCK) to drive the charge pump, meeting the limitations for the frequency divider and buffer circuit. To meet the "first" and "second" charge pump circuit limitations, Petitioner pointed to two sequential stages (transistors T23b and T23c) within Hiiragizawa’s single charge pump design.
    • Key Aspects: This anticipation argument relied on an interpretation where sequential stages of a single charge pump constitute two distinct "charge pump circuits." Petitioner asserted this interpretation is consistent with the Patent Owner's infringement contentions in related district court litigation.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 1, 3, 4, and 6-8 based on Ito (Patent 6,836,177), which discloses a multi-stage step-up circuit with frequency-divider circuits and a selector circuit.

4. Key Technical Contentions (Beyond Claim Construction)

  • Interpretation of "Charge Pump Circuit": A central contention, particularly for the Hiiragizawa and Ito grounds, was that sequential, serially connected stages within a single, larger charge pump device should be interpreted as meeting the claim limitations for a "first charge pump circuit" and a "second charge pump circuit." Petitioner argued this interpretation was supported by the Patent Owner’s own positions in co-pending litigation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 4, and 6-8 of Patent 7,969,231 as unpatentable.