PTAB

IPR2025-01453

SK Hynix Inc v. Advanced Memory Technologies LLC

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petition

1. Case Identification

2. Patent Overview

  • Title: Non-Volatile Semiconductor Memory
  • Brief Description: The ’835 patent relates to a non-volatile semiconductor memory architecture designed for simultaneously writing to multiple memory cells. The invention uses a system of M data lines, M switch circuits, and M switch control circuits to manage the application of a drain voltage to a larger number of bit lines, aiming to reduce write time.

3. Grounds for Unpatentability

Ground 1: Anticipation by Murakami - Claims 1, 2, and 4 are anticipated by Murakami under 35 U.S.C. § 102.

  • Prior Art Relied Upon: Murakami (JP Pat. Appl. Pub. No. JPH06150670A).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Murakami, which describes an EPROM/EEPROM architecture, discloses every element of independent claim 1 and dependent claims 2 and 4. Petitioner mapped Murakami’s memory array, which has multiple bit lines (e.g., D0, Dj+1) connected to a "common data line CD" via Y-gates, to the claimed structure requiring M data lines where M is less than the number of bit lines. Murakami's "charge pump circuit" supplying a VPP voltage was identified as the claimed "drain voltage generation circuit." The "variable resistance circuit VR" controlled by a "block decoder circuit DE" in Murakami was asserted to be the claimed "M switch circuits" and "M switch control circuits," respectively. The parallel MOSFETs (Q1-Q4) within the VR circuit were identified as the claimed N switches. For dependent claims, Petitioner argued that Murakami’s MOSFETs satisfy the "first conductivity type" and "connected together in parallel" limitations of claim 2, and its decoder circuit DE controls the on/off states of the switches for each data line, meeting claim 4.

Ground 2: Obviousness over Murakami and Yu - Claim 5 is obvious over Murakami in view of Yu.

  • Prior Art Relied Upon: Murakami (JP Pat. Appl. Pub. No. JPH06150670A) and Yu (Application # 2007/0263449).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that claim 5 depends from claim 1 and adds the limitation that the switch control circuits control the on-state periods of the N switches. While Murakami's decoder circuit DE controls the on/off state and voltage level based on memory cell location, Yu explicitly teaches controlling the duration (i.e., pulse width) of programming pulses to optimize the writing process in flash memory.
    • Motivation to Combine: A POSITA would combine Murakami's architecture with Yu's technique for modulating pulse duration. Both references address the same fundamental problem of improving write performance and reliability in non-volatile memory arrays. Petitioner argued a POSITA would be motivated to integrate Yu's well-understood method of controlling the on-state period into Murakami's system to achieve finer control over the programming process, thereby addressing cell-to-cell variability in addition to the location-based variability that Murakami already targets.
    • Expectation of Success: A POSITA would have an expectation of success because combining voltage level adjustment (from Murakami) and pulse duration adjustment (from Yu) were known, compatible, and predictable methods for programming NVM devices. Integrating these techniques was presented as a routine optimization.

Ground 3: Anticipation by Kobayashi - Claims 1, 4, and 5 are anticipated by Kobayashi.

  • Prior Art Relied Upon: Kobayashi (JP Pat. Appl. Pub. No. JPH0562484A).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that Kobayashi’s flash EEPROM design discloses all limitations of claims 1, 4, and 5. Kobayashi's memory array includes multiple bit lines connected to M=2 data lines (internal data transmission lines 213, 223) via Y-gate transistors, which are controlled by a column address signal. Its "program voltage generation circuit 10" supplies the drain voltage (Vpp). The "write circuits 71 and 72" and corresponding "write transistors 214 and 224" were mapped to the claimed M switch control circuits and M switch circuits, respectively. For claim 4, Petitioner argued that Kobayashi’s write circuits control the on/off states of the write transistors on a data line-by-data line basis. For claim 5, Petitioner asserted that Kobayashi’s alternative embodiment, which uses control circuits with delay elements to generate offset Vpp pulses for the write transistors, explicitly teaches controlling the "on-state periods" of the switches to suppress current peaks during simultaneous write operations.

  • Additional Grounds: Petitioner asserted claim 2 is obvious over Kobayashi in view of the general knowledge of a POSITA, who would have been motivated to implement Kobayashi's single-transistor switches with multi-fingered, parallel transistors to improve current density, reduce parasitic effects, and enhance overall performance, which was a well-known and predictable design optimization.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 2, 4, and 5 of Patent 8,400,835 as unpatentable.