PTAB

IPR2025-01456

Infineon Technologies Americas Corp v. MOSAID Technologies Inc

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petition

1. Case Identification

2. Patent Overview

  • Title: Clock Mode Determination in a Memory System
  • Brief Description: The ’028 patent describes a non-volatile memory system where memory devices are arranged in series with a memory controller. The core of the invention is a configurable memory device that includes a clock input buffer configurable to operate in either a single-ended or a differential signaling mode based on complementary clock signals.

3. Grounds for Unpatentability

Ground 1: Claims 1-4 and 10-17 are obvious over Ryu in view of Cole and Arcoleo

  • Prior Art Relied Upon: Ryu (Application # 2006/0023499), Cole (Application # 2005/0141666), and Arcoleo (Patent # 5,864,506).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ryu disclosed the foundational non-volatile memory device with memory blocks, data ports, and a chip enable signal. However, Ryu lacked specifics on clock signal configurations. Cole taught a configurable clock input buffer that could switch between single-ended and differential signaling modes using complementary input signals (xxStbP/xxStbN). This ground asserted that Cole’s discontinuous "strobe" signals meet the "clock input signal" limitations based on the Patent Owner's infringement contentions in co-pending litigation. Arcoleo taught a configurable output buffer with a plurality of selectable drive strengths to transfer output data.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Ryu and Cole to achieve interoperability between devices using different signaling standards, a known problem that Cole was designed to solve. A POSITA would further add Arcoleo's configurable output buffer to the Ryu-Cole combination to address the well-known need to match output drive strength to the electrical load of the system, thereby optimizing performance and preventing signal degradation, a solution Arcoleo explicitly provides for memory devices.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involved applying known techniques (configurable signaling and drive strength) to a known system (non-volatile memory) using conventional logic circuitry to achieve predictable results.

Ground 2: Claims 1-4 and 10-17 are obvious over Ryu, Cole, and Arcoleo in view of Grundy

  • Prior Art Relied Upon: Ryu (’499 application), Cole (’666 application), Arcoleo (’506 patent), and Grundy (Application # 2004/0148482).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 1, arguing that a true "clock signal" is a continuous, periodic signal, distinct from the discontinuous "strobe" signals taught by Cole. Petitioner argued that Grundy taught using a continuous, free-running clock signal for synchronizing data in a chained memory system, where separate control lines indicate data validity. This ground proposed modifying the Ryu-Cole-Arcoleo combination by replacing Cole’s discontinuous strobes with Grundy’s continuous clock signals.
    • Motivation to Combine: A POSITA would have recognized continuous clocks (Grundy) and discontinuous strobes (Cole) as two known and interchangeable design alternatives for timing data transfers. The choice would be an obvious substitution to meet the demands of a particular application. Grundy's continuous clock method is particularly advantageous and well-suited for serially chained memory systems, reducing complexity and cost.
    • Expectation of Success: Success was expected because substituting one known timing mechanism for another was a simple design choice with predictable outcomes. Both Ryu and Cole contemplated alternative timing schemes, indicating full compatibility with such a modification.

Ground 3: Claims 5-9 are obvious over Ryu and Cole in view of Arcoleo and Akashi

  • Prior Art Relied Upon: Ryu (’499 application), Cole (’666 application), Arcoleo (’506 patent), and Akashi (Patent # 5,917,759).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Ground 1 to address the limitations of claims 5-9, which recite configurable data input buffers using a reference voltage and terminated signals. Petitioner argued that Akashi taught a memory device with a configurable input buffer that uses an external reference voltage (VREF) to determine the logic levels of common data signals, specifically for Stub Series Terminated Logic (SSTL). Akashi’s teachings directly map to claim 5 (reference voltage), claim 6 (predetermined voltage level), claim 7 (half the high logic level), and claims 8-9 (terminated signals/SSTL).
    • Motivation to Combine: A POSITA, seeking to improve the reliability of data input in the Ryu-Cole-Arcoleo device, would have been motivated to incorporate Akashi’s teachings. Akashi provided a known solution to improve noise immunity and accurately judge data bits by using a reference voltage. Furthermore, implementing SSTL as taught by Akashi was a known method for promoting signal integrity in high-speed environments.
    • Expectation of Success: The combination was expected to succeed because it involved integrating a standard input buffer design (from Akashi) into a memory device to perform a conventional function (judging logic levels), yielding the predictable benefit of improved data integrity.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 1D) for claims 5-9 based on the combination of Ryu, Cole, Grundy, Arcoleo, and Akashi, which applied the same logic from Akashi to the continuous-clock combination established in Ground 2.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial is unwarranted and stated its intent to use the bifurcated briefing process established by the Stewart Memorandum to rebut any contrary arguments from the Patent Owner.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-17 of the ’028 patent as unpatentable.